;CodeVisionAVR C Compiler V1.0.2.2d Standard
;(C) Copyright 1998-2002 Pavel Haiduc, HP InfoTech s.r.l.
;http://www.hpinfotech.ro
;e-mail:office@hpinfotech.ro , hpinfotech@xmail.ro

;Chip type           : AT90S8535
;Clock frequency     : 4,000000 MHz
;Memory model        : Small
;Optimize for        : Size
;Internal SRAM size  : 512
;External SRAM size  : 0
;Data Stack size     : 128
;Promote char to int : No
;char is unsigned    : Yes
;Automatic register allocation : On
;Use AVR Studio Terminal I/O   : No

	.DEVICE AT90S8535
	.LISTMAC
	.EQU UDRE=0x5
	.EQU RXC=0x7
	.EQU USR=0xB
	.EQU UDR=0xC
	.EQU EERE=0x0
	.EQU EEWE=0x1
	.EQU EEMWE=0x2
	.EQU SPSR=0xE
	.EQU SPDR=0xF
	.EQU EECR=0x1C
	.EQU EEDR=0x1D
	.EQU EEARL=0x1E
	.EQU EEARH=0x1F
	.EQU WDTCR=0x21
	.EQU MCUCR=0x35
	.EQU RAMPZ=0x3B
	.EQU SPL=0x3D
	.EQU SPH=0x3E
	.EQU SREG=0x3F
	.DEF R0X0=R0
	.DEF R0X1=R1
	.DEF R0X2=R2
	.DEF R0X3=R3
	.DEF R0X4=R4
	.DEF R0X5=R5
	.DEF R0X6=R6
	.DEF R0X7=R7
	.DEF R0X8=R8
	.DEF R0X9=R9
	.DEF R0XA=R10
	.DEF R0XB=R11
	.DEF R0XC=R12
	.DEF R0XD=R13
	.DEF R0XE=R14
	.DEF R0XF=R15
	.DEF R0X10=R16
	.DEF R0X11=R17
	.DEF R0X12=R18
	.DEF R0X13=R19
	.DEF R0X14=R20
	.DEF R0X15=R21
	.DEF R0X16=R22
	.DEF R0X17=R23
	.DEF R0X18=R24
	.DEF R0X19=R25
	.DEF R0X1A=R26
	.DEF R0X1B=R27
	.DEF R0X1C=R28
	.DEF R0X1D=R29
	.DEF R0X1E=R30
	.DEF R0X1F=R31
	.EQU __se_bit=0x40
	.EQU __sm_mask=0x30
	.EQU __sm_powerdown=0x20

	.MACRO __CPD1N
	CPI  R30,LOW(@0)
	LDI  R26,HIGH(@0)
	CPC  R31,R26
	LDI  R26,BYTE3(@0)
	CPC  R22,R26
	LDI  R26,BYTE4(@0)
	CPC  R23,R26
	.ENDM

	.MACRO __CPD2N
	CPI  R26,LOW(@0)
	LDI  R30,HIGH(@0)
	CPC  R27,R30
	LDI  R30,BYTE3(@0)
	CPC  R24,R30
	LDI  R30,BYTE4(@0)
	CPC  R25,R30
	.ENDM

	.MACRO __CPWRR
	CP   R@0,R@2
	CPC  R@1,R@3
	.ENDM

	.MACRO __CPWRN
	CPI  R@0,LOW(@2)
	LDI  R30,HIGH(@2)
	CPC  R@1,R30
	.ENDM

	.MACRO __ADDD1N
	SUBI R30,LOW(-@0)
	SBCI R31,HIGH(-@0)
	SBCI R22,BYTE3(-@0)
	SBCI R23,BYTE4(-@0)
	.ENDM

	.MACRO __ADDD2N
	SUBI R26,LOW(-@0)
	SBCI R27,HIGH(-@0)
	SBCI R24,BYTE3(-@0)
	SBCI R25,BYTE4(-@0)
	.ENDM

	.MACRO __SUBD1N
	SUBI R30,LOW(@0)
	SBCI R31,HIGH(@0)
	SBCI R22,BYTE3(@0)
	SBCI R23,BYTE4(@0)
	.ENDM

	.MACRO __SUBD2N
	SUBI R26,LOW(@0)
	SBCI R27,HIGH(@0)
	SBCI R24,BYTE3(@0)
	SBCI R25,BYTE4(@0)
	.ENDM

	.MACRO __ANDD1N
	ANDI R30,LOW(@0)
	ANDI R31,HIGH(@0)
	ANDI R22,BYTE3(@0)
	ANDI R23,BYTE4(@0)
	.ENDM

	.MACRO __ORD1N
	ORI  R30,LOW(@0)
	ORI  R31,HIGH(@0)
	ORI  R22,BYTE3(@0)
	ORI  R23,BYTE4(@0)
	.ENDM

	.MACRO __DELAY_USB
	LDI  R24,LOW(@0)
__DELAY_USB_LOOP:
	DEC  R24
	BRNE __DELAY_USB_LOOP
	.ENDM

	.MACRO __DELAY_USW
	LDI  R24,LOW(@0)
	LDI  R25,HIGH(@0)
__DELAY_USW_LOOP:
	SBIW R24,1
	BRNE __DELAY_USW_LOOP
	.ENDM

	.MACRO __CLRD1S
	CLR  R30
	STD  Y+@0,R30
	STD  Y+@0+1,R30
	STD  Y+@0+2,R30
	STD  Y+@0+3,R30
	.ENDM

	.MACRO __GETD1S
	LDD  R30,Y+@0
	LDD  R31,Y+@0+1
	LDD  R22,Y+@0+2
	LDD  R23,Y+@0+3
	.ENDM

	.MACRO __PUTD1S
	STD  Y+@0,R30
	STD  Y+@0+1,R31
	STD  Y+@0+2,R22
	STD  Y+@0+3,R23
	.ENDM

	.MACRO __POINTB1MN
	LDI  R30,LOW(@0+@1)
	.ENDM

	.MACRO __POINTW1MN
	LDI  R30,LOW(@0+@1)
	LDI  R31,HIGH(@0+@1)
	.ENDM

	.MACRO __POINTW1FN
	LDI  R30,LOW(2*@0+@1)
	LDI  R31,HIGH(2*@0+@1)
	.ENDM

	.MACRO __POINTB2MN
	LDI  R26,LOW(@0+@1)
	.ENDM

	.MACRO __POINTW2MN
	LDI  R26,LOW(@0+@1)
	LDI  R27,HIGH(@0+@1)
	.ENDM

	.MACRO __GETD1N
	LDI  R30,LOW(@0)
	LDI  R31,HIGH(@0)
	LDI  R22,BYTE3(@0)
	LDI  R23,BYTE4(@0)
	.ENDM

	.MACRO __GETD2N
	LDI  R26,LOW(@0)
	LDI  R27,HIGH(@0)
	LDI  R24,BYTE3(@0)
	LDI  R25,BYTE4(@0)
	.ENDM

	.MACRO __GETD2S
	LDD  R26,Y+@0
	LDD  R27,Y+@0+1
	LDD  R24,Y+@0+2
	LDD  R25,Y+@0+3
	.ENDM

	.MACRO __GETB1MN
	LDS  R30,@0+@1
	.ENDM

	.MACRO __GETW1MN
	LDS  R30,@0+@1
	LDS  R31,@0+@1+1
	.ENDM

	.MACRO __GETD1MN
	LDS  R30,@0+@1
	LDS  R31,@0+@1+1
	LDS  R22,@0+@1+2
	LDS  R23,@0+@1+3
	.ENDM

	.MACRO __GETBRMN
	LDS  R@2,@0+@1
	.ENDM

	.MACRO __GETWRMN
	LDS  R@2,@0+@1
	LDS  R@3,@0+@1+1
	.ENDM

	.MACRO __GETB2MN
	LDS  R26,@0+@1
	.ENDM

	.MACRO __GETW2MN
	LDS  R26,@0+@1
	LDS  R27,@0+@1+1
	.ENDM

	.MACRO __GETD2MN
	LDS  R26,@0+@1
	LDS  R27,@0+@1+1
	LDS  R24,@0+@1+2
	LDS  R25,@0+@1+3
	.ENDM

	.MACRO __PUTB1MN
	STS  @0+@1,R30
	.ENDM

	.MACRO __PUTW1MN
	STS  @0+@1,R30
	STS  @0+@1+1,R31
	.ENDM

	.MACRO __PUTD1MN
	STS  @0+@1,R30
	STS  @0+@1+1,R31
	STS  @0+@1+2,R22
	STS  @0+@1+3,R23
	.ENDM

	.MACRO __PUTBMRN
	STS  @0+@1,R@2
	.ENDM

	.MACRO __PUTWMRN
	STS  @0+@1,R@2
	STS  @0+@1+1,R@3
	.ENDM

	.MACRO __GETW1R
	MOV  R30,R@0
	MOV  R31,R@1
	.ENDM

	.MACRO __GETW2R
	MOV  R26,R@0
	MOV  R27,R@1
	.ENDM

	.MACRO __GETWRN
	LDI  R@0,LOW(@2)
	LDI  R@1,HIGH(@2)
	.ENDM

	.MACRO __PUTW1R
	MOV  R@0,R30
	MOV  R@1,R31
	.ENDM

	.MACRO __ADDWRN
	SUBI R@0,LOW(-@2)
	SBCI R@1,HIGH(-@2)
	.ENDM

	.MACRO __ADDWRR
	ADD  R@0,R@2
	ADC  R@1,R@3
	.ENDM

	.MACRO __SUBWRN
	SUBI R@0,LOW(@2)
	SBCI R@1,HIGH(@2)
	.ENDM

	.MACRO __SUBWRR
	SUB  R@0,R@2
	SBC  R@1,R@3
	.ENDM

	.MACRO __ANDWRN
	ANDI R@0,LOW(@2)
	ANDI R@1,HIGH(@2)
	.ENDM

	.MACRO __ANDWRR
	AND  R@0,R@2
	AND  R@1,R@3
	.ENDM

	.MACRO __ORWRN
	ORI  R@0,LOW(@2)
	ORI  R@1,HIGH(@2)
	.ENDM

	.MACRO __ORWRR
	OR   R@0,R@2
	OR   R@1,R@3
	.ENDM

	.MACRO __EORWRR
	EOR  R@0,R@2
	EOR  R@1,R@3
	.ENDM

	.MACRO __GETWRS
	LDD  R@0,Y+@2
	LDD  R@1,Y+@2+1
	.ENDM

	.MACRO __PUTWSR
	STD  Y+@2,R@0
	STD  Y+@2+1,R@1
	.ENDM

	.MACRO __MOVEWRR
	MOV  R@0,R@2
	MOV  R@1,R@3
	.ENDM

	.MACRO __INWR
	IN   R@0,@2
	IN   R@1,@2+1
	.ENDM

	.MACRO __OUTWR
	OUT  @2+1,R@1
	OUT  @2,R@0
	.ENDM

	.MACRO __CALL1MN
	LDS  R30,@0+@1
	LDS  R31,@0+@1+1
	ICALL
	.ENDM

	.MACRO __NBST
	BST  R@0,@1
	IN   R30,SREG
	LDI  R31,0x40
	EOR  R30,R31
	OUT  SREG,R30
	.ENDM


	.MACRO __PUTB1SN
	LDD  R26,Y+@0
	LDD  R27,Y+@0+1
	SUBI R26,LOW(-@1)
	SBCI R27,HIGH(-@1)
	ST   X,R30
	.ENDM

	.MACRO __PUTW1SN
	LDD  R26,Y+@0
	LDD  R27,Y+@0+1
	SUBI R26,LOW(-@1)
	SBCI R27,HIGH(-@1)
	ST   X+,R30
	ST   X,R31
	.ENDM

	.MACRO __PUTD1SN
	LDD  R26,Y+@0
	LDD  R27,Y+@0+1
	SUBI R26,LOW(-@1)
	SBCI R27,HIGH(-@1)
	RCALL __PUTDP1
	.ENDM

	.MACRO __PUTB1SNS
	LDD  R26,Y+@0
	LDD  R27,Y+@0+1
	ADIW R26,@1
	ST   X,R30
	.ENDM

	.MACRO __PUTW1SNS
	LDD  R26,Y+@0
	LDD  R27,Y+@0+1
	ADIW R26,@1
	ST   X+,R30
	ST   X,R31
	.ENDM

	.MACRO __PUTD1SNS
	LDD  R26,Y+@0
	LDD  R27,Y+@0+1
	ADIW R26,@1
	RCALL __PUTDP1
	.ENDM

	.MACRO __PUTB1PMN
	LDS  R26,@0
	LDS  R27,@0+1
	SUBI R26,LOW(-@1)
	SBCI R27,HIGH(-@1)
	ST   X,R30
	.ENDM

	.MACRO __PUTW1PMN
	LDS  R26,@0
	LDS  R27,@0+1
	SUBI R26,LOW(-@1)
	SBCI R27,HIGH(-@1)
	ST   X+,R30
	ST   X,R31
	.ENDM

	.MACRO __PUTD1PMN
	LDS  R26,@0
	LDS  R27,@0+1
	SUBI R26,LOW(-@1)
	SBCI R27,HIGH(-@1)
	RCALL __PUTDP1
	.ENDM

	.MACRO __PUTB1PMNS
	LDS  R26,@0
	LDS  R27,@0+1
	ADIW R26,@1
	ST   X,R30
	.ENDM

	.MACRO __PUTW1PMNS
	LDS  R26,@0
	LDS  R27,@0+1
	ADIW R26,@1
	ST   X+,R30
	ST   X,R31
	.ENDM

	.MACRO __PUTD1PMNS
	LDS  R26,@0
	LDS  R27,@0+1
	ADIW R26,@1
	RCALL __PUTDP1
	.ENDM

	.MACRO __GETB1SX
	MOV  R30,R28
	MOV  R31,R29
	SUBI R30,LOW(-@0)
	SBCI R31,HIGH(-@0)
	LD   R30,Z
	.ENDM

	.MACRO __GETW1SX
	MOV  R30,R28
	MOV  R31,R29
	SUBI R30,LOW(-@0)
	SBCI R31,HIGH(-@0)
	LD   R0,Z+
	LD   R31,Z
	MOV  R30,R0
	.ENDM

	.MACRO __GETD1SX
	MOV  R30,R28
	MOV  R31,R29
	SUBI R30,LOW(-@0)
	SBCI R31,HIGH(-@0)
	LD   R0,Z+
	LD   R1,Z+
	LD   R22,Z+
	LD   R23,Z
	MOV  R30,R0
	MOV  R31,R1
	.ENDM

	.MACRO __GETB2SX
	MOV  R26,R28
	MOV  R27,R29
	SUBI R26,LOW(-@0)
	SBCI R27,HIGH(-@0)
	LD   R26,X
	.ENDM

	.MACRO __GETW2SX
	MOV  R26,R28
	MOV  R27,R29
	SUBI R26,LOW(-@0)
	SBCI R27,HIGH(-@0)
	LD   R0,X+
	LD   R27,X
	MOV  R26,R0
	.ENDM

	.MACRO __GETD2SX
	MOV  R26,R28
	MOV  R27,R29
	SUBI R26,LOW(-@0)
	SBCI R27,HIGH(-@0)
	LD   R0,X+
	LD   R1,X+
	LD   R24,X+
	LD   R25,X
	MOV  R26,R0
	MOV  R27,R1
	.ENDM

	.MACRO __GETBRSX
	MOV  R30,R28
	MOV  R31,R29
	SUBI R30,LOW(-@1)
	SBCI R31,HIGH(-@1)
	LD   R@0,Z
	.ENDM

	.MACRO __GETWRSX
	MOV  R30,R28
	MOV  R31,R29
	SUBI R30,LOW(-@2)
	SBCI R31,HIGH(-@2)
	LD   R@0,Z+
	LD   R@1,Z
	.ENDM

	.MACRO __LSLW8SX
	MOV  R30,R28
	MOV  R31,R29
	SUBI R30,LOW(-@0)
	SBCI R31,HIGH(-@0)
	LD   R31,Z
	CLR  R30
	.ENDM

	.MACRO __PUTB1SX
	MOV  R26,R28
	MOV  R27,R29
	SUBI R26,LOW(-@0)
	SBCI R27,HIGH(-@0)
	ST   X,R30
	.ENDM

	.MACRO __PUTW1SX
	MOV  R26,R28
	MOV  R27,R29
	SUBI R26,LOW(-@0)
	SBCI R27,HIGH(-@0)
	ST   X+,R30
	ST   X,R31
	.ENDM

	.MACRO __PUTD1SX
	MOV  R26,R28
	MOV  R27,R29
	SUBI R26,LOW(-@0)
	SBCI R27,HIGH(-@0)
	ST   X+,R30
	ST   X+,R31
	ST   X+,R22
	ST   X,R23
	.ENDM

	.MACRO __CLRW1SX
	MOV  R30,R28
	MOV  R31,R29
	SUBI R30,LOW(-@0)
	SBCI R31,HIGH(-@0)
	CLR  R0
	ST   Z+,R0
	ST   Z,R0
	.ENDM

	.MACRO __CLRD1SX
	MOV  R30,R28
	MOV  R31,R29
	SUBI R30,LOW(-@0)
	SBCI R31,HIGH(-@0)
	CLR  R0
	ST   Z+,R0
	ST   Z+,R0
	ST   Z+,R0
	ST   Z,R0
	.ENDM

	.MACRO __PUTB2SX
	MOV  R30,R28
	MOV  R31,R29
	SUBI R30,LOW(-@0)
	SBCI R31,HIGH(-@0)
	ST   Z,R26
	.ENDM

	.MACRO __PUTW2SX
	MOV  R30,R28
	MOV  R31,R29
	SUBI R30,LOW(-@0)
	SBCI R31,HIGH(-@0)
	ST   Z+,R26
	ST   Z,R27
	.ENDM

	.MACRO __PUTBSRX
	MOV  R30,R28
	MOV  R31,R29
	SUBI R30,LOW(-@0)
	SBCI R31,HIGH(-@0)
	ST   Z,R@1
	.ENDM

	.MACRO __PUTWSRX
	MOV  R30,R28
	MOV  R31,R29
	SUBI R30,LOW(-@2)
	SBCI R31,HIGH(-@2)
	ST   Z+,R@0
	ST   Z,R@1
	.ENDM

	.MACRO __PUTB1SNX
	MOV  R26,R28
	MOV  R27,R29
	SUBI R26,LOW(-@0)
	SBCI R27,HIGH(-@0)
	LD   R0,X+
	LD   R27,X
	MOV  R26,R0
	SUBI R26,LOW(-@1)
	SBCI R27,HIGH(-@1)
	ST   X,R30
	.ENDM

	.MACRO __PUTW1SNX
	MOV  R26,R28
	MOV  R27,R29
	SUBI R26,LOW(-@0)
	SBCI R27,HIGH(-@0)
	LD   R0,X+
	LD   R27,X
	MOV  R26,R0
	SUBI R26,LOW(-@1)
	SBCI R27,HIGH(-@1)
	ST   X+,R30
	ST   X,R31
	.ENDM

	.MACRO __PUTD1SNX
	MOV  R26,R28
	MOV  R27,R29
	SUBI R26,LOW(-@0)
	SBCI R27,HIGH(-@0)
	LD   R0,X+
	LD   R27,X
	MOV  R26,R0
	SUBI R26,LOW(-@1)
	SBCI R27,HIGH(-@1)
	ST   X+,R30
	ST   X+,R31
	ST   X+,R22
	ST   X,R23
	.ENDM

	.CSEG
	.ORG 0x11

	.INCLUDE "vtsolair.inc"

__RESET:
	CLI
	CLR  R30
	OUT  EECR,R30
	OUT  MCUCR,R30

;DISABLE WATCHDOG
	LDI  R31,0x18
	OUT  WDTCR,R31
	LDI  R31,0x10
	OUT  WDTCR,R31

;CLEAR R2-R15
	LDI  R24,14
	LDI  R26,2
	CLR  R27
__CLEAR_REG:
	ST   X+,R30
	DEC  R24
	BRNE __CLEAR_REG

;CLEAR SRAM
	LDI  R24,LOW(0x200)
	LDI  R25,HIGH(0x200)
	LDI  R26,0x60
__CLEAR_SRAM:
	ST   X+,R30
	SBIW R24,1
	BRNE __CLEAR_SRAM

;GLOBAL VARIABLES INITIALIZATION
	LDI  R30,LOW(__GLOBAL_INI_TBL*2)
	LDI  R31,HIGH(__GLOBAL_INI_TBL*2)
__GLOBAL_INI_NEXT:
	LPM
	ADIW R30,1
	MOV  R1,R0
	LPM
	ADIW R30,1
	MOV  R22,R30
	MOV  R23,R31
	MOV  R31,R0
	MOV  R30,R1
	SBIW R30,0
	BREQ __GLOBAL_INI_END
	LPM
	ADIW R30,1
	MOV  R26,R0
	LPM
	ADIW R30,1
	MOV  R27,R0
	LPM
	ADIW R30,1
	MOV  R24,R0
	LPM
	ADIW R30,1
	MOV  R25,R0
__GLOBAL_INI_LOOP:
	LPM
	ADIW R30,1
	ST   X+,R0
	SBIW R24,1
	BRNE __GLOBAL_INI_LOOP
	MOV  R30,R22
	MOV  R31,R23
	RJMP __GLOBAL_INI_NEXT
__GLOBAL_INI_END:

;STACK POINTER INITIALIZATION
	LDI  R30,LOW(0x25F)
	OUT  SPL,R30
	LDI  R30,HIGH(0x25F)
	OUT  SPH,R30

;DATA STACK POINTER INITIALIZATION
	LDI  R28,LOW(0xDF)
	LDI  R29,HIGH(0xDF)

	RJMP _main

	.ESEG
	.ORG 1

	.DSEG
	.ORG 0xE0
;       1 /*********************************************
;       2 This program was produced by the
;       3 CodeWizardAVR V1.0.2.2d Standard
;       4 Automatic Program Generator
;       5 © Copyright 1998-2002
;       6 Pavel Haiduc, HP InfoTech s.r.l.
;       7 http://www.hpinfotech.ro
;       8 e-mail:office@hpinfotech.ro , hpinfotech@xmail.ro
;       9 
;      10 Project : 
;      11 Version : 
;      12 Date    : 07/04/2003
;      13 Author  : Philippe Mariano                
;      14 Company : LYCEE Pierre Emile MARTIN       
;      15 Comments: 
;      16 
;      17 
;      18 Chip type           : AT90S8535
;      19 Clock frequency     : 4,000000 MHz
;      20 Memory model        : Small
;      21 Internal SRAM size  : 512
;      22 External SRAM size  : 0
;      23 Data Stack size     : 128
;      24 *********************************************/
;      25 
;      26 #include <90s8535.h>
;      27 // CodeVisionAVR C Compiler
;      28 // (C) 1998-2000 Pavel Haiduc, HP InfoTech S.R.L.
;      29 
;      30 // I/O registers definitions for the AT90S8535
;      31 
;      32 #ifndef _90S8535_INCLUDED_
;      33 #define _90S8535_INCLUDED_
;      34 
;      35 #pragma used+
;      36 sfrb ADCL=4;
;      37 sfrb ADCH=5;
;      38 sfrw ADCW=4;      // 16 bit access
;      39 sfrb ADCSR=6;
;      40 sfrb ADMUX=7;
;      41 sfrb ACSR=8;
;      42 sfrb UBRR=9;
;      43 sfrb UCR=0xa;
;      44 sfrb USR=0xb;
;      45 sfrb UDR=0xc;
;      46 sfrb SPCR=0xd;
;      47 sfrb SPSR=0xe;
;      48 sfrb SPDR=0xf;
;      49 sfrb PIND=0x10;
;      50 sfrb DDRD=0x11;
;      51 sfrb PORTD=0x12;
;      52 sfrb PINC=0x13;
;      53 sfrb DDRC=0x14;
;      54 sfrb PORTC=0x15;
;      55 sfrb PINB=0x16;
;      56 sfrb DDRB=0x17;
;      57 sfrb PORTB=0x18;
;      58 sfrb PINA=0x19;
;      59 sfrb DDRA=0x1a;
;      60 sfrb PORTA=0x1b;
;      61 sfrb EECR=0x1c;
;      62 sfrb EEDR=0x1d;
;      63 sfrb EEARL=0x1e;
;      64 sfrb EEARH=0x1f;
;      65 sfrw EEAR=0x1e;   // 16 bit access
;      66 sfrb WDTCR=0x21;
;      67 sfrb ASSR=0x22;
;      68 sfrb OCR2=0x23;
;      69 sfrb TCNT2=0x24;
;      70 sfrb TCCR2=0x25;
;      71 sfrb ICR1L=0x26;
;      72 sfrb ICR1H=0x27;
;      73 sfrw ICR1=0x26;   // 16 bit access
;      74 sfrb OCR1BL=0x28;
;      75 sfrb OCR1BH=0x29;
;      76 sfrw OCR1B=0x28;  // 16 bit access
;      77 sfrb OCR1AL=0x2a;
;      78 sfrb OCR1AH=0x2b;
;      79 sfrw OCR1A=0x2a;  // 16 bit access
;      80 sfrb TCNT1L=0x2c;
;      81 sfrb TCNT1H=0x2d;
;      82 sfrw TCNT1=0x2c;  // 16 bit access
;      83 sfrb TCCR1B=0x2e;
;      84 sfrb TCCR1A=0x2f;
;      85 sfrb TCNT0=0x32;
;      86 sfrb TCCR0=0x33;
;      87 sfrb MCUSR=0x34;
;      88 sfrb MCUCR=0x35;
;      89 sfrb TIFR=0x38;
;      90 sfrb TIMSK=0x39;
;      91 sfrb GIFR=0x3a;
;      92 sfrb GIMSK=0x3b;
;      93 sfrb SPL=0x3d;
;      94 sfrb SPH=0x3e;
;      95 sfrb SREG=0x3f;
;      96 #pragma used-
;      97 
;      98 // Interrupt vectors definitions
;      99 
;     100 #define EXT_INT0 2
;     101 #define EXT_INT1 3
;     102 #define TIM2_COMP 4
;     103 #define TIM2_OVF 5
;     104 #define TIM1_CAPT 6
;     105 #define TIM1_COMPA 7
;     106 #define TIM1_COMPB 8
;     107 #define TIM1_OVF 9
;     108 #define TIM0_OVF 10
;     109 #define SPI_STC 11
;     110 #define UART_RXC 12
;     111 #define UART_DRE 13
;     112 #define UART_TXC 14
;     113 #define ADC_INT 15
;     114 #define EE_RDY 16
;     115 #define ANA_COMP 17
;     116 
;     117 #endif
;     118 
;     119 #include <stdio.h>
;     120 // CodeVisionAVR C Compiler
;     121 // (C) 1998-2002 Pavel Haiduc, HP InfoTech S.R.L.
;     122 
;     123 // Prototypes for standard I/O functions
;     124 
;     125 #ifndef _STDIO_INCLUDED_
;     126 #define _STDIO_INCLUDED_
;     127 
;     128 #ifndef NULL
;     129 #define NULL 0
;     130 #endif
;     131 
;     132 #ifndef EOF
;     133 #define EOF -1
;     134 #endif
;     135 
;     136 #pragma used+
;     137 
;     138 char getchar(void);
;     139 void putchar(char c);
;     140 void puts(char *str);
;     141 void putsf(char flash *str);
;     142 
;     143 #ifdef _MODEL_TINY_
;     144 char *gets(char *str,unsigned char len);
;     145 #endif
;     146 
;     147 #ifdef _MODEL_SMALL_
;     148 char *gets(char *str,unsigned int len);
;     149 #endif
;     150 
;     151 #pragma parptr+
;     152 void printf(char flash *fmtstr);
;     153 void sprintf(char *str, char flash *fmtstr);
;     154 #pragma parptr-
;     155 
;     156 signed char scanf(char flash *fmtstr,...);
;     157 signed char sscanf(char *str, char flash *fmtstr,...);
;     158 
;     159 #ifdef _DEBUG_TERMINAL_IO_
;     160 // Used for AVR Studio Terminal I/O
;     161 // DON'T CHANGE!
;     162 #pragma warn-
;     163 #pragma keep+
;     164 void _c_getchar(void) {}
;     165 
;     166 char getchar(void)
;     167 {
;     168 #asm
;     169      push  r16
;     170      push  r17
;     171 __getchar0:
;     172 #endasm
;     173 _c_getchar();
;     174 #asm
;     175      cpi   r17,0xff
;     176      breq  __getchar0
;     177      mov   r30,r16
;     178      pop   r17
;     179      pop   r16
;     180 #endasm
;     181 }
;     182 
;     183 void _c_putchar(void) {}
;     184 
;     185 void putchar(char c)
;     186 {
;     187 #asm
;     188     mov   r30,r16
;     189     ld    r16,y
;     190 #endasm
;     191 _c_putchar();
;     192 #asm
;     193     mov   r16,r30
;     194 #endasm
;     195 }
;     196 #pragma keep-
;     197 
;     198 #ifdef _WARNINGS_ON_
;     199 #pragma warn+
;     200 #endif
;     201 
;     202 #endif
;     203 #pragma used-
;     204 
;     205 #pragma library stdio.lib
;     206 
;     207 #endif
;     208 
;     209 
;     210 #define arret 0
;     211 #define marche 1
;     212 #define ralentit 2
;     213 
;     214 
;     215 // Read the AD conversion result
;     216 unsigned int read_adc(unsigned char adc_input)
;     217 {

	.CSEG
_read_adc:
;     218 ADMUX=adc_input;
	LD   R30,Y
	OUT  0x7,R30
;     219 // Start the AD conversion
;     220 ADCSR|=0x40;
	SBI  0x6,6
;     221 // Wait for the AD conversion to complete
;     222 while ((ADCSR & 0x10)==0);
_0xB:
	SBIS 0x6,4
	RJMP _0xB
;     223 ADCSR|=0x10;
	SBI  0x6,4
;     224 return ADCW;
	IN   R30,0x4
	IN   R31,0x4+1
	ADIW R28,1
	RET
;     225 }
;     226 
;     227 // Declare your global variables here
;     228 
;     229 void main(void)
;     230 {
_main:
;     231 // Declare your local variables here
;     232 unsigned char etat=arret;
;     233 int TENSION;
;     234 
;     235 // Input/Output Ports initialization
;     236 // Port A
;     237 PORTA=0x00;
;	etat -> R16
;	TENSION -> R17,R18
	LDI  R16,0
	CLR  R30
	OUT  0x1B,R30
;     238 DDRA=0x00;
	OUT  0x1A,R30
;     239 
;     240 // Port B
;     241 PORTB=0x00;
	RCALL SUBOPT_0x0
;     242 DDRB=0x1f;
	LDI  R30,LOW(31)
	OUT  0x17,R30
;     243 
;     244 // Port C
;     245 PORTC=0x00;
	CLR  R30
	OUT  0x15,R30
;     246 DDRC=0x00;
	OUT  0x14,R30
;     247 
;     248 // Port D
;     249 PORTD=0x00;
	OUT  0x12,R30
;     250 DDRD=0x20;
	LDI  R30,LOW(32)
	OUT  0x11,R30
;     251 
;     252 // Timer/Counter 0 initialization
;     253 // Clock source: System Clock
;     254 // Clock value: Timer 0 Stopped
;     255 TCCR0=0x00;
	CLR  R30
	OUT  0x33,R30
;     256 TCNT0=0x00;
	OUT  0x32,R30
;     257 
;     258 // Timer/Counter 1 initialization
;     259 // Clock source: System Clock
;     260 // Clock value: 4000,000 kHz
;     261 // Mode: Ph. correct PWM top=00FFh
;     262 // OC1A output: Non-Inv.
;     263 // OC1B output: Discon.
;     264 // Noise Canceler: Off
;     265 // Input Capture on Falling Edge
;     266 TCCR1A=0x81;
	LDI  R30,LOW(129)
	OUT  0x2F,R30
;     267 TCCR1B=0x01;
	LDI  R30,LOW(1)
	OUT  0x2E,R30
;     268 TCNT1H=0x00;
	CLR  R30
	OUT  0x2D,R30
;     269 TCNT1L=0x00;
	OUT  0x2C,R30
;     270 OCR1AH=0x00;
	OUT  0x2B,R30
;     271 OCR1AL=0x00;
	OUT  0x2A,R30
;     272 OCR1BH=0x00;
	OUT  0x29,R30
;     273 OCR1BL=0x00;
	OUT  0x28,R30
;     274 
;     275 // Timer/Counter 2 initialization
;     276 // Clock source: System Clock
;     277 // Clock value: Timer 2 Stopped
;     278 // Mode: Normal top=FFh
;     279 // OC2 output: Disconnected
;     280 TCCR2=0x00;
	OUT  0x25,R30
;     281 ASSR=0x00;
	OUT  0x22,R30
;     282 TCNT2=0x00;
	OUT  0x24,R30
;     283 OCR2=0x00;
	OUT  0x23,R30
;     284 
;     285 // External Interrupt(s) initialization
;     286 // INT0: Off
;     287 // INT1: Off
;     288 GIMSK=0x00;
	OUT  0x3B,R30
;     289 MCUCR=0x00;
	OUT  0x35,R30
;     290 
;     291 // Timer(s)/Counter(s) Interrupt(s) initialization
;     292 TIMSK=0x00;
	OUT  0x39,R30
;     293 
;     294 // Analog Comparator initialization
;     295 // Analog Comparator: Off
;     296 // Analog Comparator Input Capture by Timer/Counter 1: Off
;     297 // Analog Comparator Output: Off
;     298 ACSR=0x80;
	LDI  R30,LOW(128)
	OUT  0x8,R30
;     299 
;     300 // ADC initialization
;     301 // ADC Clock frequency: 31,250 kHz
;     302 ADCSR=0x87;
	LDI  R30,LOW(135)
	OUT  0x6,R30
;     303 
;     304 while (1)
_0xF:
;     305       { 
;     306 
;     307       TENSION=read_adc(6);
	LDI  R30,LOW(6)
	ST   -Y,R30
	RCALL _read_adc
	__PUTW1R 17,18
;     308       TENSION = (TENSION/4)*10; 
	__GETW1R 17,18
	RCALL __ASRW2
	LDI  R26,LOW(10)
	LDI  R27,HIGH(10)
	RCALL __MULW12
	__PUTW1R 17,18
;     309 
;     310       switch (etat)
	MOV  R30,R16
;     311 	{
;     312 	
;     313       		case arret : PORTB = 0;OCR1A=245;
	CPI  R30,0
	BRNE _0x15
	RCALL SUBOPT_0x0
	LDI  R30,LOW(245)
	LDI  R31,HIGH(245)
	OUT  0x2A+1,R31
	OUT  0x2A,R30
;     314       	       		if ((TENSION>816) || (TENSION==816)) etat = marche;
	RCALL SUBOPT_0x1
	BRLT _0x17
	RCALL SUBOPT_0x1
	BRNE _0x16
_0x17:
	LDI  R16,LOW(1)
;     315       	       			else etat = arret;
	RJMP _0x19
_0x16:
	LDI  R16,LOW(0)
_0x19:
;     316      		 break;
	RJMP _0x14
;     317       
;     318       		case marche : PORTB = 3;OCR1A=5;
_0x15:
	CPI  R30,LOW(0x1)
	BRNE _0x1A
	LDI  R30,LOW(3)
	OUT  0x18,R30
	LDI  R30,LOW(5)
	LDI  R31,HIGH(5)
	OUT  0x2A+1,R31
	OUT  0x2A,R30
;     319       			if (TENSION<765) etat = ralentit;
	__CPWRN 17,18,765
	BRGE _0x1B
	LDI  R16,LOW(2)
;     320       				else etat = marche;
	RJMP _0x1C
_0x1B:
	LDI  R16,LOW(1)
_0x1C:
;     321      		break;
	RJMP _0x14
;     322       
;     323       		case ralentit : PORTB = 1; OCR1A=127;
_0x1A:
	CPI  R30,LOW(0x2)
	BRNE _0x14
	LDI  R30,LOW(1)
	OUT  0x18,R30
	LDI  R30,LOW(127)
	LDI  R31,HIGH(127)
	OUT  0x2A+1,R31
	OUT  0x2A,R30
;     324       			if (TENSION<714) etat = arret;
	__CPWRN 17,18,714
	BRGE _0x1E
	LDI  R16,LOW(0)
;     325       				else if	((TENSION>816) || (TENSION==816)) etat = marche;	
	RJMP _0x1F
_0x1E:
	RCALL SUBOPT_0x1
	BRLT _0x21
	RCALL SUBOPT_0x1
	BRNE _0x20
_0x21:
	LDI  R16,LOW(1)
;     326       					else etat = ralentit;
	RJMP _0x23
_0x20:
	LDI  R16,LOW(2)
_0x23:
_0x1F:
;     327       		break;
;     328          } 
_0x14:
;     329      }; 
	RJMP _0xF
;     330 }
_0x24:
	RJMP _0x24
_getchar:
     sbis usr,rxc
     rjmp _getchar
     in   r30,udr
	RET
_putchar:
     sbis usr,udre
     rjmp _putchar
     ld   r30,y
     out  udr,r30
	ADIW R28,1
	RET

	.DSEG
_cc_G2:
	.BYTE 0x1
_pp_G2:
	.BYTE 0x2

	.CSEG

;OPTIMIZER ADDED SUBROUTINE, CALLED 2 TIMES
SUBOPT_0x0:
	CLR  R30
	OUT  0x18,R30
	RET

;OPTIMIZER ADDED SUBROUTINE, CALLED 4 TIMES
SUBOPT_0x1:
	LDI  R30,LOW(816)
	LDI  R31,HIGH(816)
	CP   R30,R17
	CPC  R31,R18
	RET

_isdigit:
	ldi  r30,1
	ld   r31,y+
	cpi  r31,'0'
	brlo __isdigit0
	cpi  r31,'9'+1
	brlo __isdigit1
__isdigit0:
	clr  r30
__isdigit1:
	ret

_isspace:
	ldi  r30,1
	ld   r31,y+
	cpi  r31,' '
	breq __isspace1
	cpi  r31,9
	breq __isspace1
	cpi  r31,13
	breq __isspace1
	clr  r30
__isspace1:
	ret

__ANEGW1:
	COM  R30
	COM  R31
	ADIW R30,1
	RET

__ASRW2:
	ASR  R31
	ROR  R30
	ASR  R31
	ROR  R30
	RET

__MULW12U:
	MOV  R0,R26
	MOV  R1,R27
	LDI  R24,17
	CLR  R26
	SUB  R27,R27
	RJMP __MULW12U1
__MULW12U3:
	BRCC __MULW12U2
	ADD  R26,R0
	ADC  R27,R1
__MULW12U2:
	LSR  R27
	ROR  R26
__MULW12U1:
	ROR  R31
	ROR  R30
	DEC  R24
	BRNE __MULW12U3
	RET

__MULW12:
	RCALL __CHKSIGNW
	RCALL __MULW12U
	BRTC __MULW121
	RCALL __ANEGW1
__MULW121:
	RET

__CHKSIGNW:
	CLT
	SBRS R31,7
	RJMP __CHKSW1
	RCALL __ANEGW1
	SET
__CHKSW1:
	SBRS R27,7
	RJMP __CHKSW2
	COM  R26
	COM  R27
	ADIW R26,1
	BLD  R0,0
	INC  R0
	BST  R0,0
__CHKSW2:
	RET

	.ORG 0x00

;INTERRUPT VECTORS
	RJMP __RESET
	RJMP 0
	RJMP 0
	RJMP 0
	RJMP 0
	RJMP 0
	RJMP 0
	RJMP 0
	RJMP 0
	RJMP 0
	RJMP 0
	RJMP 0
	RJMP 0
	RJMP 0
	RJMP 0
	RJMP 0
	RJMP 0
