;CodeVisionAVR C Compiler V1.24.0 Standard
;(C) Copyright 1998-2003 HP InfoTech s.r.l.
;http://www.hpinfotech.ro
;e-mail:office@hpinfotech.ro

;Chip type           : ATmega32
;Program type        : Application
;Clock frequency     : 8,000000 MHz
;Memory model        : Small
;Optimize for        : Size
;(s)printf features  : int, width
;(s)scanf features   : long, width
;External SRAM size  : 0
;Data Stack size     : 512 byte(s)
;Heap size           : 0 byte(s)
;Promote char to int : No
;char is unsigned    : Yes
;8 bit enums         : Yes
;Enhanced core instructions    : On
;Automatic register allocation : On

	.LISTMAC
	.EQU UDRE=0x5
	.EQU RXC=0x7
	.EQU USR=0xB
	.EQU UDR=0xC
	.EQU EERE=0x0
	.EQU EEWE=0x1
	.EQU EEMWE=0x2
	.EQU SPSR=0xE
	.EQU SPDR=0xF
	.EQU EECR=0x1C
	.EQU EEDR=0x1D
	.EQU EEARL=0x1E
	.EQU EEARH=0x1F
	.EQU WDTCR=0x21
	.EQU MCUCR=0x35
	.EQU GICR=0x3B
	.EQU SPL=0x3D
	.EQU SPH=0x3E
	.EQU SREG=0x3F

	.DEF R0X0=R0
	.DEF R0X1=R1
	.DEF R0X2=R2
	.DEF R0X3=R3
	.DEF R0X4=R4
	.DEF R0X5=R5
	.DEF R0X6=R6
	.DEF R0X7=R7
	.DEF R0X8=R8
	.DEF R0X9=R9
	.DEF R0XA=R10
	.DEF R0XB=R11
	.DEF R0XC=R12
	.DEF R0XD=R13
	.DEF R0XE=R14
	.DEF R0XF=R15
	.DEF R0X10=R16
	.DEF R0X11=R17
	.DEF R0X12=R18
	.DEF R0X13=R19
	.DEF R0X14=R20
	.DEF R0X15=R21
	.DEF R0X16=R22
	.DEF R0X17=R23
	.DEF R0X18=R24
	.DEF R0X19=R25
	.DEF R0X1A=R26
	.DEF R0X1B=R27
	.DEF R0X1C=R28
	.DEF R0X1D=R29
	.DEF R0X1E=R30
	.DEF R0X1F=R31

	.EQU __se_bit=0x80
	.EQU __sm_mask=0x70
	.EQU __sm_adc_noise_red=0x10
	.EQU __sm_powerdown=0x20
	.EQU __sm_powersave=0x30
	.EQU __sm_standby=0x60
	.EQU __sm_ext_standby=0x70

	.MACRO __CPD1N
	CPI  R30,LOW(@0)
	LDI  R26,HIGH(@0)
	CPC  R31,R26
	LDI  R26,BYTE3(@0)
	CPC  R22,R26
	LDI  R26,BYTE4(@0)
	CPC  R23,R26
	.ENDM

	.MACRO __CPD2N
	CPI  R26,LOW(@0)
	LDI  R30,HIGH(@0)
	CPC  R27,R30
	LDI  R30,BYTE3(@0)
	CPC  R24,R30
	LDI  R30,BYTE4(@0)
	CPC  R25,R30
	.ENDM

	.MACRO __CPWRR
	CP   R@0,R@2
	CPC  R@1,R@3
	.ENDM

	.MACRO __CPWRN
	CPI  R@0,LOW(@2)
	LDI  R30,HIGH(@2)
	CPC  R@1,R30
	.ENDM

	.MACRO __ADDD1N
	SUBI R30,LOW(-@0)
	SBCI R31,HIGH(-@0)
	SBCI R22,BYTE3(-@0)
	SBCI R23,BYTE4(-@0)
	.ENDM

	.MACRO __ADDD2N
	SUBI R26,LOW(-@0)
	SBCI R27,HIGH(-@0)
	SBCI R24,BYTE3(-@0)
	SBCI R25,BYTE4(-@0)
	.ENDM

	.MACRO __SUBD1N
	SUBI R30,LOW(@0)
	SBCI R31,HIGH(@0)
	SBCI R22,BYTE3(@0)
	SBCI R23,BYTE4(@0)
	.ENDM

	.MACRO __SUBD2N
	SUBI R26,LOW(@0)
	SBCI R27,HIGH(@0)
	SBCI R24,BYTE3(@0)
	SBCI R25,BYTE4(@0)
	.ENDM

	.MACRO __ANDD1N
	ANDI R30,LOW(@0)
	ANDI R31,HIGH(@0)
	ANDI R22,BYTE3(@0)
	ANDI R23,BYTE4(@0)
	.ENDM

	.MACRO __ORD1N
	ORI  R30,LOW(@0)
	ORI  R31,HIGH(@0)
	ORI  R22,BYTE3(@0)
	ORI  R23,BYTE4(@0)
	.ENDM

	.MACRO __DELAY_USB
	LDI  R24,LOW(@0)
__DELAY_USB_LOOP:
	DEC  R24
	BRNE __DELAY_USB_LOOP
	.ENDM

	.MACRO __DELAY_USW
	LDI  R24,LOW(@0)
	LDI  R25,HIGH(@0)
__DELAY_USW_LOOP:
	SBIW R24,1
	BRNE __DELAY_USW_LOOP
	.ENDM

	.MACRO __CLRD1S
	CLR  R30
	STD  Y+@0,R30
	STD  Y+@0+1,R30
	STD  Y+@0+2,R30
	STD  Y+@0+3,R30
	.ENDM

	.MACRO __GETD1S
	LDD  R30,Y+@0
	LDD  R31,Y+@0+1
	LDD  R22,Y+@0+2
	LDD  R23,Y+@0+3
	.ENDM

	.MACRO __PUTD1S
	STD  Y+@0,R30
	STD  Y+@0+1,R31
	STD  Y+@0+2,R22
	STD  Y+@0+3,R23
	.ENDM

	.MACRO __POINTB1MN
	LDI  R30,LOW(@0+@1)
	.ENDM

	.MACRO __POINTW1MN
	LDI  R30,LOW(@0+@1)
	LDI  R31,HIGH(@0+@1)
	.ENDM

	.MACRO __POINTW1FN
	LDI  R30,LOW(2*@0+@1)
	LDI  R31,HIGH(2*@0+@1)
	.ENDM

	.MACRO __POINTB2MN
	LDI  R26,LOW(@0+@1)
	.ENDM

	.MACRO __POINTW2MN
	LDI  R26,LOW(@0+@1)
	LDI  R27,HIGH(@0+@1)
	.ENDM

	.MACRO __GETD1N
	LDI  R30,LOW(@0)
	LDI  R31,HIGH(@0)
	LDI  R22,BYTE3(@0)
	LDI  R23,BYTE4(@0)
	.ENDM

	.MACRO __GETD2N
	LDI  R26,LOW(@0)
	LDI  R27,HIGH(@0)
	LDI  R24,BYTE3(@0)
	LDI  R25,BYTE4(@0)
	.ENDM

	.MACRO __GETD2S
	LDD  R26,Y+@0
	LDD  R27,Y+@0+1
	LDD  R24,Y+@0+2
	LDD  R25,Y+@0+3
	.ENDM

	.MACRO __GETB1MN
	LDS  R30,@0+@1
	.ENDM

	.MACRO __GETW1MN
	LDS  R30,@0+@1
	LDS  R31,@0+@1+1
	.ENDM

	.MACRO __GETD1MN
	LDS  R30,@0+@1
	LDS  R31,@0+@1+1
	LDS  R22,@0+@1+2
	LDS  R23,@0+@1+3
	.ENDM

	.MACRO __GETBRMN
	LDS  R@2,@0+@1
	.ENDM

	.MACRO __GETWRMN
	LDS  R@2,@0+@1
	LDS  R@3,@0+@1+1
	.ENDM

	.MACRO __GETB2MN
	LDS  R26,@0+@1
	.ENDM

	.MACRO __GETW2MN
	LDS  R26,@0+@1
	LDS  R27,@0+@1+1
	.ENDM

	.MACRO __GETD2MN
	LDS  R26,@0+@1
	LDS  R27,@0+@1+1
	LDS  R24,@0+@1+2
	LDS  R25,@0+@1+3
	.ENDM

	.MACRO __PUTB1MN
	STS  @0+@1,R30
	.ENDM

	.MACRO __PUTW1MN
	STS  @0+@1,R30
	STS  @0+@1+1,R31
	.ENDM

	.MACRO __PUTD1MN
	STS  @0+@1,R30
	STS  @0+@1+1,R31
	STS  @0+@1+2,R22
	STS  @0+@1+3,R23
	.ENDM

	.MACRO __PUTBMRN
	STS  @0+@1,R@2
	.ENDM

	.MACRO __PUTWMRN
	STS  @0+@1,R@2
	STS  @0+@1+1,R@3
	.ENDM

	.MACRO __GETW1R
	MOV  R30,R@0
	MOV  R31,R@1
	.ENDM

	.MACRO __GETW2R
	MOV  R26,R@0
	MOV  R27,R@1
	.ENDM

	.MACRO __GETWRN
	LDI  R@0,LOW(@2)
	LDI  R@1,HIGH(@2)
	.ENDM

	.MACRO __PUTW1R
	MOV  R@0,R30
	MOV  R@1,R31
	.ENDM

	.MACRO __PUTW2R
	MOV  R@0,R26
	MOV  R@1,R27
	.ENDM

	.MACRO __ADDWRN
	SUBI R@0,LOW(-@2)
	SBCI R@1,HIGH(-@2)
	.ENDM

	.MACRO __ADDWRR
	ADD  R@0,R@2
	ADC  R@1,R@3
	.ENDM

	.MACRO __SUBWRN
	SUBI R@0,LOW(@2)
	SBCI R@1,HIGH(@2)
	.ENDM

	.MACRO __SUBWRR
	SUB  R@0,R@2
	SBC  R@1,R@3
	.ENDM

	.MACRO __ANDWRN
	ANDI R@0,LOW(@2)
	ANDI R@1,HIGH(@2)
	.ENDM

	.MACRO __ANDWRR
	AND  R@0,R@2
	AND  R@1,R@3
	.ENDM

	.MACRO __ORWRN
	ORI  R@0,LOW(@2)
	ORI  R@1,HIGH(@2)
	.ENDM

	.MACRO __ORWRR
	OR   R@0,R@2
	OR   R@1,R@3
	.ENDM

	.MACRO __EORWRR
	EOR  R@0,R@2
	EOR  R@1,R@3
	.ENDM

	.MACRO __GETWRS
	LDD  R@0,Y+@2
	LDD  R@1,Y+@2+1
	.ENDM

	.MACRO __PUTWSR
	STD  Y+@2,R@0
	STD  Y+@2+1,R@1
	.ENDM

	.MACRO __MOVEWRR
	MOV  R@0,R@2
	MOV  R@1,R@3
	.ENDM

	.MACRO __INWR
	IN   R@0,@2
	IN   R@1,@2+1
	.ENDM

	.MACRO __OUTWR
	OUT  @2+1,R@1
	OUT  @2,R@0
	.ENDM

	.MACRO __CALL1MN
	LDS  R30,@0+@1
	LDS  R31,@0+@1+1
	ICALL
	.ENDM

	.MACRO __NBST
	BST  R@0,@1
	IN   R30,SREG
	LDI  R31,0x40
	EOR  R30,R31
	OUT  SREG,R30
	.ENDM


	.MACRO __PUTB1SN
	LDD  R26,Y+@0
	LDD  R27,Y+@0+1
	SUBI R26,LOW(-@1)
	SBCI R27,HIGH(-@1)
	ST   X,R30
	.ENDM

	.MACRO __PUTW1SN
	LDD  R26,Y+@0
	LDD  R27,Y+@0+1
	SUBI R26,LOW(-@1)
	SBCI R27,HIGH(-@1)
	ST   X+,R30
	ST   X,R31
	.ENDM

	.MACRO __PUTD1SN
	LDD  R26,Y+@0
	LDD  R27,Y+@0+1
	SUBI R26,LOW(-@1)
	SBCI R27,HIGH(-@1)
	CALL __PUTDP1
	.ENDM

	.MACRO __PUTB1SNS
	LDD  R26,Y+@0
	LDD  R27,Y+@0+1
	ADIW R26,@1
	ST   X,R30
	.ENDM

	.MACRO __PUTW1SNS
	LDD  R26,Y+@0
	LDD  R27,Y+@0+1
	ADIW R26,@1
	ST   X+,R30
	ST   X,R31
	.ENDM

	.MACRO __PUTD1SNS
	LDD  R26,Y+@0
	LDD  R27,Y+@0+1
	ADIW R26,@1
	CALL __PUTDP1
	.ENDM

	.MACRO __PUTB1PMN
	LDS  R26,@0
	LDS  R27,@0+1
	SUBI R26,LOW(-@1)
	SBCI R27,HIGH(-@1)
	ST   X,R30
	.ENDM

	.MACRO __PUTW1PMN
	LDS  R26,@0
	LDS  R27,@0+1
	SUBI R26,LOW(-@1)
	SBCI R27,HIGH(-@1)
	ST   X+,R30
	ST   X,R31
	.ENDM

	.MACRO __PUTD1PMN
	LDS  R26,@0
	LDS  R27,@0+1
	SUBI R26,LOW(-@1)
	SBCI R27,HIGH(-@1)
	CALL __PUTDP1
	.ENDM

	.MACRO __PUTB1PMNS
	LDS  R26,@0
	LDS  R27,@0+1
	ADIW R26,@1
	ST   X,R30
	.ENDM

	.MACRO __PUTW1PMNS
	LDS  R26,@0
	LDS  R27,@0+1
	ADIW R26,@1
	ST   X+,R30
	ST   X,R31
	.ENDM

	.MACRO __PUTD1PMNS
	LDS  R26,@0
	LDS  R27,@0+1
	ADIW R26,@1
	CALL __PUTDP1
	.ENDM

	.MACRO __GETB1SX
	MOVW R30,R28
	SUBI R30,LOW(-@0)
	SBCI R31,HIGH(-@0)
	LD   R30,Z
	.ENDM

	.MACRO __GETW1SX
	MOVW R30,R28
	SUBI R30,LOW(-@0)
	SBCI R31,HIGH(-@0)
	LD   R0,Z+
	LD   R31,Z
	MOV  R30,R0
	.ENDM

	.MACRO __GETD1SX
	MOVW R30,R28
	SUBI R30,LOW(-@0)
	SBCI R31,HIGH(-@0)
	LD   R0,Z+
	LD   R1,Z+
	LD   R22,Z+
	LD   R23,Z
	MOVW R30,R0
	.ENDM

	.MACRO __GETB2SX
	MOVW R26,R28
	SUBI R26,LOW(-@0)
	SBCI R27,HIGH(-@0)
	LD   R26,X
	.ENDM

	.MACRO __GETW2SX
	MOVW R26,R28
	SUBI R26,LOW(-@0)
	SBCI R27,HIGH(-@0)
	LD   R0,X+
	LD   R27,X
	MOV  R26,R0
	.ENDM

	.MACRO __GETD2SX
	MOVW R26,R28
	SUBI R26,LOW(-@0)
	SBCI R27,HIGH(-@0)
	LD   R0,X+
	LD   R1,X+
	LD   R24,X+
	LD   R25,X
	MOVW R26,R0
	.ENDM

	.MACRO __GETBRSX
	MOVW R30,R28
	SUBI R30,LOW(-@1)
	SBCI R31,HIGH(-@1)
	LD   R@0,Z
	.ENDM

	.MACRO __GETWRSX
	MOVW R30,R28
	SUBI R30,LOW(-@2)
	SBCI R31,HIGH(-@2)
	LD   R@0,Z+
	LD   R@1,Z
	.ENDM

	.MACRO __LSLW8SX
	MOVW R30,R28
	SUBI R30,LOW(-@0)
	SBCI R31,HIGH(-@0)
	LD   R31,Z
	CLR  R30
	.ENDM

	.MACRO __PUTB1SX
	MOVW R26,R28
	SUBI R26,LOW(-@0)
	SBCI R27,HIGH(-@0)
	ST   X,R30
	.ENDM

	.MACRO __PUTW1SX
	MOVW R26,R28
	SUBI R26,LOW(-@0)
	SBCI R27,HIGH(-@0)
	ST   X+,R30
	ST   X,R31
	.ENDM

	.MACRO __PUTD1SX
	MOVW R26,R28
	SUBI R26,LOW(-@0)
	SBCI R27,HIGH(-@0)
	ST   X+,R30
	ST   X+,R31
	ST   X+,R22
	ST   X,R23
	.ENDM

	.MACRO __CLRW1SX
	MOVW R30,R28
	SUBI R30,LOW(-@0)
	SBCI R31,HIGH(-@0)
	CLR  R0
	ST   Z+,R0
	ST   Z,R0
	.ENDM

	.MACRO __CLRD1SX
	MOVW R30,R28
	SUBI R30,LOW(-@0)
	SBCI R31,HIGH(-@0)
	CLR  R0
	ST   Z+,R0
	ST   Z+,R0
	ST   Z+,R0
	ST   Z,R0
	.ENDM

	.MACRO __PUTB2SX
	MOVW R30,R28
	SUBI R30,LOW(-@0)
	SBCI R31,HIGH(-@0)
	ST   Z,R26
	.ENDM

	.MACRO __PUTW2SX
	MOVW R30,R28
	SUBI R30,LOW(-@0)
	SBCI R31,HIGH(-@0)
	ST   Z+,R26
	ST   Z,R27
	.ENDM

	.MACRO __PUTBSRX
	MOVW R30,R28
	SUBI R30,LOW(-@0)
	SBCI R31,HIGH(-@0)
	ST   Z,R@1
	.ENDM

	.MACRO __PUTWSRX
	MOVW R30,R28
	SUBI R30,LOW(-@2)
	SBCI R31,HIGH(-@2)
	ST   Z+,R@0
	ST   Z,R@1
	.ENDM

	.MACRO __PUTB1SNX
	MOVW R26,R28
	SUBI R26,LOW(-@0)
	SBCI R27,HIGH(-@0)
	LD   R0,X+
	LD   R27,X
	MOV  R26,R0
	SUBI R26,LOW(-@1)
	SBCI R27,HIGH(-@1)
	ST   X,R30
	.ENDM

	.MACRO __PUTW1SNX
	MOVW R26,R28
	SUBI R26,LOW(-@0)
	SBCI R27,HIGH(-@0)
	LD   R0,X+
	LD   R27,X
	MOV  R26,R0
	SUBI R26,LOW(-@1)
	SBCI R27,HIGH(-@1)
	ST   X+,R30
	ST   X,R31
	.ENDM

	.MACRO __PUTD1SNX
	MOVW R26,R28
	SUBI R26,LOW(-@0)
	SBCI R27,HIGH(-@0)
	LD   R0,X+
	LD   R27,X
	MOV  R26,R0
	SUBI R26,LOW(-@1)
	SBCI R27,HIGH(-@1)
	ST   X+,R30
	ST   X+,R31
	ST   X+,R22
	ST   X,R23
	.ENDM

	.MACRO __MULBRR
	MULS R@0,R@1
	MOV  R30,R0
	.ENDM

	.MACRO __MULBRRU
	MUL  R@0,R@1
	MOV  R30,R0
	.ENDM

	.CSEG
	.ORG 0

	.INCLUDE "com32.vec"
	.INCLUDE "com32.inc"

__RESET:
	CLI
	CLR  R30
	OUT  EECR,R30

;INTERRUPT VECTORS ARE PLACED
;AT THE START OF FLASH
	LDI  R31,1
	OUT  GICR,R31
	OUT  GICR,R30
	OUT  MCUCR,R30

;DISABLE WATCHDOG
	LDI  R31,0x18
	OUT  WDTCR,R31
	LDI  R31,0x10
	OUT  WDTCR,R31

;CLEAR R2-R14
	LDI  R24,13
	LDI  R26,2
	CLR  R27
__CLEAR_REG:
	ST   X+,R30
	DEC  R24
	BRNE __CLEAR_REG

;CLEAR SRAM
	LDI  R24,LOW(0x800)
	LDI  R25,HIGH(0x800)
	LDI  R26,0x60
__CLEAR_SRAM:
	ST   X+,R30
	SBIW R24,1
	BRNE __CLEAR_SRAM

;GLOBAL VARIABLES INITIALIZATION
	LDI  R30,LOW(__GLOBAL_INI_TBL*2)
	LDI  R31,HIGH(__GLOBAL_INI_TBL*2)
__GLOBAL_INI_NEXT:
	LPM  R0,Z+
	LPM  R1,Z+
	MOVW R22,R30
	MOVW R30,R0
	SBIW R30,0
	BREQ __GLOBAL_INI_END
	LPM  R26,Z+
	LPM  R27,Z+
	LPM  R24,Z+
	LPM  R25,Z+
__GLOBAL_INI_LOOP:
	LPM  R0,Z+
	ST   X+,R0
	SBIW R24,1
	BRNE __GLOBAL_INI_LOOP
	MOVW R30,R22
	RJMP __GLOBAL_INI_NEXT
__GLOBAL_INI_END:

;STACK POINTER INITIALIZATION
	LDI  R30,LOW(0x85F)
	OUT  SPL,R30
	LDI  R30,HIGH(0x85F)
	OUT  SPH,R30

;DATA STACK POINTER INITIALIZATION
	LDI  R28,LOW(0x260)
	LDI  R29,HIGH(0x260)

	JMP  _main

	.ESEG
	.ORG 0

	.DSEG
	.ORG 0x260
;       1 /*********************************************
;       2 This program was produced by the
;       3 CodeWizardAVR V1.24.0 Standard
;       4 Automatic Program Generator
;       5 © Copyright 1998-2003 HP InfoTech s.r.l.
;       6 http://www.hpinfotech.ro
;       7 e-mail:office@hpinfotech.ro
;       8 
;       9 Project : 
;      10 Version : V6
;      11 Date    : 12/03/2006
;      12 Author  : Philippe Mariano                
;      13 Company : LYCEE Pierre Emile MARTIN       
;      14 Comments: 
;      15 
;      16 
;      17 Chip type           : ATmega32
;      18 Program type        : Application
;      19 Clock frequency     : 8,000000 MHz
;      20 Memory model        : Small
;      21 External SRAM size  : 0
;      22 Data Stack size     : 512
;      23 *********************************************/
;      24 
;      25 #include <mega32.h>
;      26 #include <delay.h>
;      27 #include <stdlib.h>
;      28 
;      29 // Alphanumeric LCD Module functions
;      30 #asm
;      31    .equ __lcd_port=0x15
   .equ __lcd_port=0x15
;      32 #endasm

;      33 #include <lcd.h>
;      34 
;      35 #define RXB8 1
;      36 #define TXB8 0
;      37 #define UPE 2
;      38 #define OVR 3
;      39 #define FE 4
;      40 #define UDRE 5
;      41 #define RXC 7
;      42 
;      43 #define FRAMING_ERROR (1<<FE)
;      44 #define PARITY_ERROR (1<<UPE)
;      45 #define DATA_OVERRUN (1<<OVR)
;      46 #define DATA_REGISTER_EMPTY (1<<UDRE)
;      47 #define RX_COMPLETE (1<<RXC)
;      48 
;      49 // Get a character from the USART Receiver
;      50 #ifndef _DEBUG_TERMINAL_IO_
;      51 #define _ALTERNATE_GETCHAR_
;      52 #pragma used+
;      53 char getchar(void)
;      54 {

	.CSEG
_getchar:
;      55 char status,data;
;      56 while (1)
	ST   -Y,R17
	ST   -Y,R16
;	status -> R16
;	data -> R17
_0x1B:
;      57       {
;      58       while (((status=UCSRA) & RX_COMPLETE)==0);
_0x1E:
	IN   R30,0xB
	MOV  R16,R30
	ANDI R30,LOW(0x80)
	BREQ _0x1E
;      59       data=UDR;
	IN   R17,12
;      60       if ((status & (FRAMING_ERROR |  DATA_OVERRUN))==0)
	MOV  R30,R16
	ANDI R30,LOW(0x18)
	BRNE _0x21
;      61          return data;
	MOV  R30,R17
	RJMP _0x8E
;      62       };
_0x21:
	RJMP _0x1B
;      63 }
_0x8E:
	LD   R16,Y+
	LD   R17,Y+
	RET
;      64 #pragma used-
;      65 #endif
;      66 
;      67 
;      68 // Standard Input/Output functions
;      69 #include <stdio.h>
;      70 
;      71 // Declare your global variables here
;      72 
;      73 void main(void)
;      74 {
_main:
;      75 // Declare your local variables here
;      76 unsigned char k1,k2,k3,k4,k5,status,erreur; 
;      77 unsigned char chaine[3];
;      78 unsigned int cmpt,cmpt_canaux,canal_base;
;      79 
;      80 PORTA=0x3F;
	SBIW R28,10
;	k1 -> R16
;	k2 -> R17
;	k3 -> R18
;	k4 -> R19
;	k5 -> R20
;	status -> R21
;	erreur -> Y+9
;	chaine -> Y+6
;	cmpt -> Y+4
;	cmpt_canaux -> Y+2
;	canal_base -> Y+0
	LDI  R30,LOW(63)
	OUT  0x1B,R30
;      81 DDRA=0x00;
	CLR  R30
	OUT  0x1A,R30
;      82 
;      83 DDRB=0x1f;
	LDI  R30,LOW(31)
	OUT  0x17,R30
;      84 
;      85 // Timer/Counter 1 initialization
;      86 // Clock source: System Clock
;      87 // Clock value: Timer 1 Stopped
;      88 // Mode: Normal top=FFFFh
;      89 // OC1A output: Discon.
;      90 // OC1B output: Discon.
;      91 // Noise Canceler: Off
;      92 // Input Capture on Falling Edge
;      93 TCCR1A=0x00;
	CLR  R30
	OUT  0x2F,R30
;      94 TCCR1B=0x00;
	OUT  0x2E,R30
;      95 TCNT1H=0x00;
	OUT  0x2D,R30
;      96 TCNT1L=0x00;
	OUT  0x2C,R30
;      97 OCR1AH=0x00;
	OUT  0x2B,R30
;      98 OCR1AL=0x00;
	OUT  0x2A,R30
;      99 OCR1BH=0x00;
	OUT  0x29,R30
;     100 OCR1BL=0x00;
	OUT  0x28,R30
;     101 
;     102 // Timer(s)/Counter(s) Interrupt(s) initialization
;     103 TIMSK=0x00;
	OUT  0x39,R30
;     104 
;     105 // USART initialization
;     106 // Communication Parameters: 8 Data, 2 Stop, No Parity
;     107 // USART Receiver: On
;     108 // USART Transmitter: Off
;     109 // USART Mode: Asynchronous
;     110 // USART Baud rate: 250000
;     111 UCSRA=0x00;
	OUT  0xB,R30
;     112 UCSRB=0x00;// Désactivation RX
	OUT  0xA,R30
;     113 UCSRC=0x8E;
	LDI  R30,LOW(142)
	OUT  0x20,R30
;     114 UBRRH=0x00;
	CLR  R30
	OUT  0x20,R30
;     115 UBRRL=0x03;
	LDI  R30,LOW(3)
	OUT  0x9,R30
;     116 
;     117 // LCD module initialization
;     118 lcd_init(16);
	LDI  R30,LOW(16)
	ST   -Y,R30
	CALL _lcd_init
;     119  
;     120   
;     121 canal_base = (~(PORTA|0xFFA0)&0x003F);
	IN   R30,0x1B
	MOVW R26,R30
	CLR  R27
	LDI  R30,LOW(65440)
	LDI  R31,HIGH(65440)
	OR   R30,R26
	OR   R31,R27
	COM  R30
	COM  R31
	ANDI R30,LOW(0x3F)
	ANDI R31,HIGH(0x3F)
	ST   Y,R30
	STD  Y+1,R31
;     122 
;     123 while (1)
_0x2E:
;     124       {  
;     125 suite:   
_0x31:
;     126 	cmpt=0;cmpt_canaux=0;erreur=0;  // Recannaissance BREAK	 
	CLR  R30
	STD  Y+4,R30
	STD  Y+4+1,R30
	CLR  R30
	STD  Y+2,R30
	STD  Y+2+1,R30
	CLR  R30
	STD  Y+9,R30
;     127          while (PIND.0 == 0);     // Attente front Montant sur RX
_0x32:
	SBIS 0x10,0
	RJMP _0x32
;     128          while (PIND.0 == 1);     // Attente front descendant sur RX
_0x35:
	SBIC 0x10,0
	RJMP _0x35
;     129          do                       // Mesure du  BREAK (pour 130us, cmpt = 158)
_0x39:
;     130          cmpt++;  
	LDD  R30,Y+4
	LDD  R31,Y+4+1
	ADIW R30,1
	STD  Y+4,R30
	STD  Y+4+1,R31
;     131          while (PIND.0==0);
	SBIS 0x10,0
	RJMP _0x39
;     132              
;     133          if (cmpt>90)    // Si Break valide 
	LDD  R26,Y+4
	LDD  R27,Y+4+1
	LDI  R30,LOW(90)
	LDI  R31,HIGH(90)
	CP   R30,R26
	CPC  R31,R27
	BRLO PC+3
	JMP _0x3B
;     134            {      
;     135            	UCSRB=0x10; // activation RX
	LDI  R30,LOW(16)
	OUT  0xA,R30
;     136                 while (cmpt_canaux < canal_base)// Attente n° canal 
_0x3C:
	LD   R30,Y
	LDD  R31,Y+1
	LDD  R26,Y+2
	LDD  R27,Y+2+1
	CP   R26,R30
	CPC  R27,R31
	BRSH _0x3E
;     137                 {
;     138                    while (((status=UCSRA) & RX_COMPLETE)==0);
_0x3F:
	IN   R30,0xB
	MOV  R21,R30
	ANDI R30,LOW(0x80)
	BREQ _0x3F
;     139                    
;     140                    if ((status & (FRAMING_ERROR |  DATA_OVERRUN |  PARITY_ERROR))==0)
	MOV  R30,R21
	ANDI R30,LOW(0x1C)
	BRNE _0x42
;     141       		        {k1=UDR;cmpt_canaux++;}
	IN   R16,12
	LDD  R30,Y+2
	LDD  R31,Y+2+1
	ADIW R30,1
	STD  Y+2,R30
	STD  Y+2+1,R31
;     142       		     	  else {PORTB.4=1;delay_us(10);PORTB.4 =0; UCSRB=0x00; goto suite;}       
	RJMP _0x43
_0x42:
	SBI  0x18,4
	__DELAY_USB 27
	CBI  0x18,4
	CLR  R30
	OUT  0xA,R30
	RJMP _0x31
_0x43:
;     143                 }
	RJMP _0x3C
_0x3E:
;     144                                  //Lecture des canaux destinés au recepteur    
;     145                                  
;     146   
;     147          	k2 = getchar();   
	CALL _getchar
	MOV  R17,R30
;     148                 k3 = getchar(); 
	CALL _getchar
	MOV  R18,R30
;     149                 k4 = getchar();
	CALL _getchar
	MOV  R19,R30
;     150                 k5 = getchar();
	CALL _getchar
	MOV  R20,R30
;     151                        			UCSRB=0x00; // Désactivation RX  
	CLR  R30
	OUT  0xA,R30
;     152                  	
;     153 	   lcd_clear();  
	CALL _lcd_clear
;     154 	   itoa((int)canal_base,chaine);lcd_puts(chaine);lcd_gotoxy(0,1);
	LD   R30,Y
	LDD  R31,Y+1
	CALL SUBOPT_0x0
	CLR  R30
	CALL SUBOPT_0x1
;     155            itoa((int)k2,chaine);lcd_puts(chaine);lcd_gotoxy(4,1);
	MOV  R30,R17
	CLR  R31
	CALL SUBOPT_0x0
	LDI  R30,LOW(4)
	CALL SUBOPT_0x1
;     156            itoa((int)k3,chaine);lcd_puts(chaine);lcd_gotoxy(8,1);
	MOV  R30,R18
	CLR  R31
	CALL SUBOPT_0x0
	LDI  R30,LOW(8)
	CALL SUBOPT_0x1
;     157            itoa((int)k4,chaine);lcd_puts(chaine);lcd_gotoxy(12,1);
	MOV  R30,R19
	CLR  R31
	CALL SUBOPT_0x0
	LDI  R30,LOW(12)
	CALL SUBOPT_0x1
;     158            itoa((int)k5,chaine);lcd_puts(chaine);
	MOV  R30,R20
	CLR  R31
	CALL SUBOPT_0x0
;     159            if (k2 <130) PORTB.3 =0; else PORTB.3 =1;
	CPI  R17,130
	BRSH _0x44
	CBI  0x18,3
	RJMP _0x45
_0x44:
	SBI  0x18,3
_0x45:
;     160            if (k3 <130) PORTB.2 =0; else PORTB.2 =1;
	CPI  R18,130
	BRSH _0x46
	CBI  0x18,2
	RJMP _0x47
_0x46:
	SBI  0x18,2
_0x47:
;     161            if (k4 <130) PORTB.1 =0; else PORTB.1 =1;
	CPI  R19,130
	BRSH _0x48
	CBI  0x18,1
	RJMP _0x49
_0x48:
	SBI  0x18,1
_0x49:
;     162            if (k5 <130) PORTB.0 =0; else PORTB.0 =1;  
	CPI  R20,130
	BRSH _0x4A
	CBI  0x18,0
	RJMP _0x4B
_0x4A:
	SBI  0x18,0
_0x4B:
;     163            k2 = k3 = k4 = k5 = 0;
	CLR  R30
	MOV  R20,R30
	MOV  R19,R30
	MOV  R18,R30
	MOV  R17,R30
;     164            delay_ms(800);   
	LDI  R30,LOW(800)
	LDI  R31,HIGH(800)
	ST   -Y,R31
	ST   -Y,R30
	CALL _delay_ms
;     165                 
;     166          }
;     167          
;     168      };
_0x3B:
	RJMP _0x2E
;     169 }
	ADIW R28,10
_0x4C:
	RJMP _0x4C
    .equ __lcd_direction=__lcd_port-1
    .equ __lcd_pin=__lcd_port-2
    .equ __lcd_rs=0
    .equ __lcd_rd=1
    .equ __lcd_enable=2
    .equ __lcd_busy_flag=7

	.DSEG
__base_y_G3:
	.BYTE 0x4

	.CSEG
__lcd_ready:
    in    r26,__lcd_direction
    andi  r26,0xf                 ;set as input
    out   __lcd_direction,r26
    sbi   __lcd_port,__lcd_rd     ;RD=1
    cbi   __lcd_port,__lcd_rs     ;RS=0
__lcd_busy:
    rcall __lcd_delay
    sbi   __lcd_port,__lcd_enable ;EN=1
    rcall __lcd_delay
    in    r26,__lcd_pin
    cbi   __lcd_port,__lcd_enable ;EN=0
    rcall __lcd_delay
    sbi   __lcd_port,__lcd_enable ;EN=1
    rcall __lcd_delay
    cbi   __lcd_port,__lcd_enable ;EN=0
    sbrc  r26,__lcd_busy_flag
    rjmp  __lcd_busy
	RET
__lcd_write_nibble:
    andi  r26,0xf0
    or    r26,r27
    out   __lcd_port,r26          ;write
    sbi   __lcd_port,__lcd_enable ;EN=1
    rcall __lcd_delay
    cbi   __lcd_port,__lcd_enable ;EN=0
__lcd_delay:
    ldi   r31,15
__lcd_delay0:
    dec   r31
    brne  __lcd_delay0
    ret
__lcd_write_data:
    cbi  __lcd_port,__lcd_rd 	  ;RD=0
    in    r26,__lcd_direction
    ori   r26,0xf7                ;set as output
    out   __lcd_direction,r26
    in    r27,__lcd_port
    andi  r27,0xf
    ld    r26,y
    rcall __lcd_write_nibble      ;RD=0, write MSN
    ld    r26,y
    swap  r26
    rcall __lcd_write_nibble      ;write LSN
    sbi   __lcd_port,__lcd_rd     ;RD=1
	ADIW R28,1
	RET
__lcd_read_nibble:
    sbi   __lcd_port,__lcd_enable ;EN=1
    rcall __lcd_delay
    in    r30,__lcd_pin           ;read
    cbi   __lcd_port,__lcd_enable ;EN=0
    rcall __lcd_delay
    andi  r30,0xf0
    ret
_lcd_read_byte0_G3:
    rcall __lcd_delay
    rcall __lcd_read_nibble       ;read MSN
    mov   r26,r30
    rcall __lcd_read_nibble       ;read LSN
    cbi   __lcd_port,__lcd_rd     ;RD=0
    swap  r30
    or    r30,r26
	RET
_lcd_gotoxy:
	CALL __lcd_ready
	LD   R30,Y
	CLR  R31
	SUBI R30,LOW(-__base_y_G3)
	SBCI R31,HIGH(-__base_y_G3)
	LD   R30,Z
	LDD  R26,Y+1
	ADD  R30,R26
	ST   -Y,R30
	CALL __lcd_write_data
	LDD  R4,Y+1
	LDD  R5,Y+0
	ADIW R28,2
	RET
_lcd_clear:
	CALL __lcd_ready
	LDI  R30,LOW(2)
	CALL SUBOPT_0x2
	LDI  R30,LOW(12)
	CALL SUBOPT_0x2
	LDI  R30,LOW(1)
	ST   -Y,R30
	CALL __lcd_write_data
	CLR  R30
	MOV  R5,R30
	MOV  R4,R30
	RET
_lcd_putchar:
    push r30
    push r31
    ld   r26,y
    set
    cpi  r26,10
    breq __lcd_putchar1
    clt
	INC  R4
	CP   R6,R4
	BRSH _0x53
	__lcd_putchar1:
	INC  R5
	CLR  R30
	ST   -Y,R30
	ST   -Y,R5
	CALL _lcd_gotoxy
	brts __lcd_putchar0
_0x53:
    rcall __lcd_ready
    sbi  __lcd_port,__lcd_rs ;RS=1
    ld   r26,y
    st   -y,r26
    rcall __lcd_write_data
__lcd_putchar0:
    pop  r31
    pop  r30
	ADIW R28,1
	RET
_lcd_puts:
    ldd  r31,y+1
    ld   r30,y
__lcd_puts0:
    ld   r26,z+
    tst  r26
    breq __lcd_puts1
    st   -y,r26    
    rcall _lcd_putchar
    rjmp __lcd_puts0
__lcd_puts1:
	ADIW R28,2
	RET
__long_delay_G3:
    clr   r26
    clr   r27
__long_delay0:
    sbiw  r26,1         ;2 cycles
    brne  __long_delay0 ;2 cycles
	RET
__lcd_init_write_G3:
    cbi  __lcd_port,__lcd_rd 	  ;RD=0
    in    r26,__lcd_direction
    ori   r26,0xf7                ;set as output
    out   __lcd_direction,r26
    in    r27,__lcd_port
    andi  r27,0xf
    ld    r26,y
    rcall __lcd_write_nibble      ;RD=0, write MSN
    sbi   __lcd_port,__lcd_rd     ;RD=1
	ADIW R28,1
	RET
_lcd_init:
    cbi   __lcd_port,__lcd_enable ;EN=0
    cbi   __lcd_port,__lcd_rs     ;RS=0
	LDD  R6,Y+0
	LD   R30,Y
	SUBI R30,-LOW(128)
	__PUTB1MN __base_y_G3,2
	LD   R30,Y
	SUBI R30,-LOW(192)
	__PUTB1MN __base_y_G3,3
	CALL SUBOPT_0x3
	CALL SUBOPT_0x3
	CALL SUBOPT_0x3
	CALL __long_delay_G3
	LDI  R30,LOW(32)
	ST   -Y,R30
	CALL __lcd_init_write_G3
	CALL __long_delay_G3
	LDI  R30,LOW(40)
	CALL SUBOPT_0x4
	LDI  R30,LOW(4)
	CALL SUBOPT_0x4
	LDI  R30,LOW(133)
	CALL SUBOPT_0x4
    in    r26,__lcd_direction
    andi  r26,0xf                 ;set as input
    out   __lcd_direction,r26
    sbi   __lcd_port,__lcd_rd     ;RD=1
	CALL _lcd_read_byte0_G3
	CPI  R30,LOW(0x5)
	BREQ _0x58
	CLR  R30
	RJMP _0x8D
_0x58:
	CALL __lcd_ready
	LDI  R30,LOW(6)
	ST   -Y,R30
	CALL __lcd_write_data
	CALL _lcd_clear
	LDI  R30,LOW(1)
_0x8D:
	ADIW R28,1
	RET
_putchar:
     sbis usr,udre
     rjmp _putchar
     ld   r30,y
     out  udr,r30
	ADIW R28,1
	RET

;OPTIMIZER ADDED SUBROUTINE, CALLED 5 TIMES
SUBOPT_0x0:
	ST   -Y,R31
	ST   -Y,R30
	MOVW R30,R28
	ADIW R30,8
	ST   -Y,R31
	ST   -Y,R30
	CALL _itoa
	MOVW R30,R28
	ADIW R30,6
	ST   -Y,R31
	ST   -Y,R30
	JMP  _lcd_puts

;OPTIMIZER ADDED SUBROUTINE, CALLED 4 TIMES
SUBOPT_0x1:
	ST   -Y,R30
	LDI  R30,LOW(1)
	ST   -Y,R30
	JMP  _lcd_gotoxy

;OPTIMIZER ADDED SUBROUTINE, CALLED 2 TIMES
SUBOPT_0x2:
	ST   -Y,R30
	CALL __lcd_write_data
	JMP  __lcd_ready

;OPTIMIZER ADDED SUBROUTINE, CALLED 3 TIMES
SUBOPT_0x3:
	CALL __long_delay_G3
	LDI  R30,LOW(48)
	ST   -Y,R30
	JMP  __lcd_init_write_G3

;OPTIMIZER ADDED SUBROUTINE, CALLED 3 TIMES
SUBOPT_0x4:
	ST   -Y,R30
	CALL __lcd_write_data
	JMP  __long_delay_G3

_itoa:
	ld   r26,y+
	ld   r27,y+
	ld   r30,y+
	ld   r31,y+
	adiw r30,0
	brpl __itoa0
	com  r30
	com  r31
	adiw r30,1
	ldi  r22,'-'
	st   x+,r22
__itoa0:
	clt
	ldi  r24,low(10000)
	ldi  r25,high(10000)
	rcall __itoa1
	ldi  r24,low(1000)
	ldi  r25,high(1000)
	rcall __itoa1
	ldi  r24,100
	clr  r25
	rcall __itoa1
	ldi  r24,10
	rcall __itoa1
	mov  r22,r30
	rcall __itoa5
	clr  r22
	st   x,r22
	ret
__itoa1:
	clr	 r22
__itoa2:
	cp   r30,r24
	cpc  r31,r25
	brlo __itoa3
	inc  r22
	sub  r30,r24
	sbc  r31,r25
	brne __itoa2
__itoa3:
	tst  r22
	brne __itoa4
	brts __itoa5
	ret
__itoa4:
	set
__itoa5:
	subi r22,-0x30
	st   x+,r22
	ret

_delay_ms:
	ld   r30,y+
	ld   r31,y+
	adiw r30,0
	breq __delay_ms1
__delay_ms0:
	__DELAY_USW 0x7D0
	wdr
	sbiw r30,1
	brne __delay_ms0
__delay_ms1:
	ret

