;CodeVisionAVR C Compiler V1.24.0 Standard
;(C) Copyright 1998-2003 HP InfoTech s.r.l.
;http://www.hpinfotech.ro
;e-mail:office@hpinfotech.ro

;Chip type           : AT90S8535
;Clock frequency     : 4,000000 MHz
;Memory model        : Small
;Optimize for        : Size
;(s)printf features  : int, width
;(s)scanf features   : long, width
;External SRAM size  : 0
;Data Stack size     : 128 byte(s)
;Heap size           : 0 byte(s)
;Promote char to int : No
;char is unsigned    : Yes
;8 bit enums         : Yes
;Automatic register allocation : On

	.DEVICE AT90S8535
	.LISTMAC
	.EQU UDRE=0x5
	.EQU RXC=0x7
	.EQU USR=0xB
	.EQU UDR=0xC
	.EQU EERE=0x0
	.EQU EEWE=0x1
	.EQU EEMWE=0x2
	.EQU SPSR=0xE
	.EQU SPDR=0xF
	.EQU EECR=0x1C
	.EQU EEDR=0x1D
	.EQU EEARL=0x1E
	.EQU EEARH=0x1F
	.EQU WDTCR=0x21
	.EQU MCUCR=0x35
	.EQU RAMPZ=0x3B
	.EQU SPL=0x3D
	.EQU SPH=0x3E
	.EQU SREG=0x3F

	.DEF R0X0=R0
	.DEF R0X1=R1
	.DEF R0X2=R2
	.DEF R0X3=R3
	.DEF R0X4=R4
	.DEF R0X5=R5
	.DEF R0X6=R6
	.DEF R0X7=R7
	.DEF R0X8=R8
	.DEF R0X9=R9
	.DEF R0XA=R10
	.DEF R0XB=R11
	.DEF R0XC=R12
	.DEF R0XD=R13
	.DEF R0XE=R14
	.DEF R0XF=R15
	.DEF R0X10=R16
	.DEF R0X11=R17
	.DEF R0X12=R18
	.DEF R0X13=R19
	.DEF R0X14=R20
	.DEF R0X15=R21
	.DEF R0X16=R22
	.DEF R0X17=R23
	.DEF R0X18=R24
	.DEF R0X19=R25
	.DEF R0X1A=R26
	.DEF R0X1B=R27
	.DEF R0X1C=R28
	.DEF R0X1D=R29
	.DEF R0X1E=R30
	.DEF R0X1F=R31

	.EQU __se_bit=0x40
	.EQU __sm_mask=0x30
	.EQU __sm_powerdown=0x20

	.MACRO __CPD1N
	CPI  R30,LOW(@0)
	LDI  R26,HIGH(@0)
	CPC  R31,R26
	LDI  R26,BYTE3(@0)
	CPC  R22,R26
	LDI  R26,BYTE4(@0)
	CPC  R23,R26
	.ENDM

	.MACRO __CPD2N
	CPI  R26,LOW(@0)
	LDI  R30,HIGH(@0)
	CPC  R27,R30
	LDI  R30,BYTE3(@0)
	CPC  R24,R30
	LDI  R30,BYTE4(@0)
	CPC  R25,R30
	.ENDM

	.MACRO __CPWRR
	CP   R@0,R@2
	CPC  R@1,R@3
	.ENDM

	.MACRO __CPWRN
	CPI  R@0,LOW(@2)
	LDI  R30,HIGH(@2)
	CPC  R@1,R30
	.ENDM

	.MACRO __ADDD1N
	SUBI R30,LOW(-@0)
	SBCI R31,HIGH(-@0)
	SBCI R22,BYTE3(-@0)
	SBCI R23,BYTE4(-@0)
	.ENDM

	.MACRO __ADDD2N
	SUBI R26,LOW(-@0)
	SBCI R27,HIGH(-@0)
	SBCI R24,BYTE3(-@0)
	SBCI R25,BYTE4(-@0)
	.ENDM

	.MACRO __SUBD1N
	SUBI R30,LOW(@0)
	SBCI R31,HIGH(@0)
	SBCI R22,BYTE3(@0)
	SBCI R23,BYTE4(@0)
	.ENDM

	.MACRO __SUBD2N
	SUBI R26,LOW(@0)
	SBCI R27,HIGH(@0)
	SBCI R24,BYTE3(@0)
	SBCI R25,BYTE4(@0)
	.ENDM

	.MACRO __ANDD1N
	ANDI R30,LOW(@0)
	ANDI R31,HIGH(@0)
	ANDI R22,BYTE3(@0)
	ANDI R23,BYTE4(@0)
	.ENDM

	.MACRO __ORD1N
	ORI  R30,LOW(@0)
	ORI  R31,HIGH(@0)
	ORI  R22,BYTE3(@0)
	ORI  R23,BYTE4(@0)
	.ENDM

	.MACRO __DELAY_USB
	LDI  R24,LOW(@0)
__DELAY_USB_LOOP:
	DEC  R24
	BRNE __DELAY_USB_LOOP
	.ENDM

	.MACRO __DELAY_USW
	LDI  R24,LOW(@0)
	LDI  R25,HIGH(@0)
__DELAY_USW_LOOP:
	SBIW R24,1
	BRNE __DELAY_USW_LOOP
	.ENDM

	.MACRO __CLRD1S
	CLR  R30
	STD  Y+@0,R30
	STD  Y+@0+1,R30
	STD  Y+@0+2,R30
	STD  Y+@0+3,R30
	.ENDM

	.MACRO __GETD1S
	LDD  R30,Y+@0
	LDD  R31,Y+@0+1
	LDD  R22,Y+@0+2
	LDD  R23,Y+@0+3
	.ENDM

	.MACRO __PUTD1S
	STD  Y+@0,R30
	STD  Y+@0+1,R31
	STD  Y+@0+2,R22
	STD  Y+@0+3,R23
	.ENDM

	.MACRO __POINTB1MN
	LDI  R30,LOW(@0+@1)
	.ENDM

	.MACRO __POINTW1MN
	LDI  R30,LOW(@0+@1)
	LDI  R31,HIGH(@0+@1)
	.ENDM

	.MACRO __POINTW1FN
	LDI  R30,LOW(2*@0+@1)
	LDI  R31,HIGH(2*@0+@1)
	.ENDM

	.MACRO __POINTB2MN
	LDI  R26,LOW(@0+@1)
	.ENDM

	.MACRO __POINTW2MN
	LDI  R26,LOW(@0+@1)
	LDI  R27,HIGH(@0+@1)
	.ENDM

	.MACRO __GETD1N
	LDI  R30,LOW(@0)
	LDI  R31,HIGH(@0)
	LDI  R22,BYTE3(@0)
	LDI  R23,BYTE4(@0)
	.ENDM

	.MACRO __GETD2N
	LDI  R26,LOW(@0)
	LDI  R27,HIGH(@0)
	LDI  R24,BYTE3(@0)
	LDI  R25,BYTE4(@0)
	.ENDM

	.MACRO __GETD2S
	LDD  R26,Y+@0
	LDD  R27,Y+@0+1
	LDD  R24,Y+@0+2
	LDD  R25,Y+@0+3
	.ENDM

	.MACRO __GETB1MN
	LDS  R30,@0+@1
	.ENDM

	.MACRO __GETW1MN
	LDS  R30,@0+@1
	LDS  R31,@0+@1+1
	.ENDM

	.MACRO __GETD1MN
	LDS  R30,@0+@1
	LDS  R31,@0+@1+1
	LDS  R22,@0+@1+2
	LDS  R23,@0+@1+3
	.ENDM

	.MACRO __GETBRMN
	LDS  R@2,@0+@1
	.ENDM

	.MACRO __GETWRMN
	LDS  R@2,@0+@1
	LDS  R@3,@0+@1+1
	.ENDM

	.MACRO __GETB2MN
	LDS  R26,@0+@1
	.ENDM

	.MACRO __GETW2MN
	LDS  R26,@0+@1
	LDS  R27,@0+@1+1
	.ENDM

	.MACRO __GETD2MN
	LDS  R26,@0+@1
	LDS  R27,@0+@1+1
	LDS  R24,@0+@1+2
	LDS  R25,@0+@1+3
	.ENDM

	.MACRO __PUTB1MN
	STS  @0+@1,R30
	.ENDM

	.MACRO __PUTW1MN
	STS  @0+@1,R30
	STS  @0+@1+1,R31
	.ENDM

	.MACRO __PUTD1MN
	STS  @0+@1,R30
	STS  @0+@1+1,R31
	STS  @0+@1+2,R22
	STS  @0+@1+3,R23
	.ENDM

	.MACRO __PUTBMRN
	STS  @0+@1,R@2
	.ENDM

	.MACRO __PUTWMRN
	STS  @0+@1,R@2
	STS  @0+@1+1,R@3
	.ENDM

	.MACRO __GETW1R
	MOV  R30,R@0
	MOV  R31,R@1
	.ENDM

	.MACRO __GETW2R
	MOV  R26,R@0
	MOV  R27,R@1
	.ENDM

	.MACRO __GETWRN
	LDI  R@0,LOW(@2)
	LDI  R@1,HIGH(@2)
	.ENDM

	.MACRO __PUTW1R
	MOV  R@0,R30
	MOV  R@1,R31
	.ENDM

	.MACRO __PUTW2R
	MOV  R@0,R26
	MOV  R@1,R27
	.ENDM

	.MACRO __ADDWRN
	SUBI R@0,LOW(-@2)
	SBCI R@1,HIGH(-@2)
	.ENDM

	.MACRO __ADDWRR
	ADD  R@0,R@2
	ADC  R@1,R@3
	.ENDM

	.MACRO __SUBWRN
	SUBI R@0,LOW(@2)
	SBCI R@1,HIGH(@2)
	.ENDM

	.MACRO __SUBWRR
	SUB  R@0,R@2
	SBC  R@1,R@3
	.ENDM

	.MACRO __ANDWRN
	ANDI R@0,LOW(@2)
	ANDI R@1,HIGH(@2)
	.ENDM

	.MACRO __ANDWRR
	AND  R@0,R@2
	AND  R@1,R@3
	.ENDM

	.MACRO __ORWRN
	ORI  R@0,LOW(@2)
	ORI  R@1,HIGH(@2)
	.ENDM

	.MACRO __ORWRR
	OR   R@0,R@2
	OR   R@1,R@3
	.ENDM

	.MACRO __EORWRR
	EOR  R@0,R@2
	EOR  R@1,R@3
	.ENDM

	.MACRO __GETWRS
	LDD  R@0,Y+@2
	LDD  R@1,Y+@2+1
	.ENDM

	.MACRO __PUTWSR
	STD  Y+@2,R@0
	STD  Y+@2+1,R@1
	.ENDM

	.MACRO __MOVEWRR
	MOV  R@0,R@2
	MOV  R@1,R@3
	.ENDM

	.MACRO __INWR
	IN   R@0,@2
	IN   R@1,@2+1
	.ENDM

	.MACRO __OUTWR
	OUT  @2+1,R@1
	OUT  @2,R@0
	.ENDM

	.MACRO __CALL1MN
	LDS  R30,@0+@1
	LDS  R31,@0+@1+1
	ICALL
	.ENDM

	.MACRO __NBST
	BST  R@0,@1
	IN   R30,SREG
	LDI  R31,0x40
	EOR  R30,R31
	OUT  SREG,R30
	.ENDM


	.MACRO __PUTB1SN
	LDD  R26,Y+@0
	LDD  R27,Y+@0+1
	SUBI R26,LOW(-@1)
	SBCI R27,HIGH(-@1)
	ST   X,R30
	.ENDM

	.MACRO __PUTW1SN
	LDD  R26,Y+@0
	LDD  R27,Y+@0+1
	SUBI R26,LOW(-@1)
	SBCI R27,HIGH(-@1)
	ST   X+,R30
	ST   X,R31
	.ENDM

	.MACRO __PUTD1SN
	LDD  R26,Y+@0
	LDD  R27,Y+@0+1
	SUBI R26,LOW(-@1)
	SBCI R27,HIGH(-@1)
	RCALL __PUTDP1
	.ENDM

	.MACRO __PUTB1SNS
	LDD  R26,Y+@0
	LDD  R27,Y+@0+1
	ADIW R26,@1
	ST   X,R30
	.ENDM

	.MACRO __PUTW1SNS
	LDD  R26,Y+@0
	LDD  R27,Y+@0+1
	ADIW R26,@1
	ST   X+,R30
	ST   X,R31
	.ENDM

	.MACRO __PUTD1SNS
	LDD  R26,Y+@0
	LDD  R27,Y+@0+1
	ADIW R26,@1
	RCALL __PUTDP1
	.ENDM

	.MACRO __PUTB1PMN
	LDS  R26,@0
	LDS  R27,@0+1
	SUBI R26,LOW(-@1)
	SBCI R27,HIGH(-@1)
	ST   X,R30
	.ENDM

	.MACRO __PUTW1PMN
	LDS  R26,@0
	LDS  R27,@0+1
	SUBI R26,LOW(-@1)
	SBCI R27,HIGH(-@1)
	ST   X+,R30
	ST   X,R31
	.ENDM

	.MACRO __PUTD1PMN
	LDS  R26,@0
	LDS  R27,@0+1
	SUBI R26,LOW(-@1)
	SBCI R27,HIGH(-@1)
	RCALL __PUTDP1
	.ENDM

	.MACRO __PUTB1PMNS
	LDS  R26,@0
	LDS  R27,@0+1
	ADIW R26,@1
	ST   X,R30
	.ENDM

	.MACRO __PUTW1PMNS
	LDS  R26,@0
	LDS  R27,@0+1
	ADIW R26,@1
	ST   X+,R30
	ST   X,R31
	.ENDM

	.MACRO __PUTD1PMNS
	LDS  R26,@0
	LDS  R27,@0+1
	ADIW R26,@1
	RCALL __PUTDP1
	.ENDM

	.MACRO __GETB1SX
	MOV  R30,R28
	MOV  R31,R29
	SUBI R30,LOW(-@0)
	SBCI R31,HIGH(-@0)
	LD   R30,Z
	.ENDM

	.MACRO __GETW1SX
	MOV  R30,R28
	MOV  R31,R29
	SUBI R30,LOW(-@0)
	SBCI R31,HIGH(-@0)
	LD   R0,Z+
	LD   R31,Z
	MOV  R30,R0
	.ENDM

	.MACRO __GETD1SX
	MOV  R30,R28
	MOV  R31,R29
	SUBI R30,LOW(-@0)
	SBCI R31,HIGH(-@0)
	LD   R0,Z+
	LD   R1,Z+
	LD   R22,Z+
	LD   R23,Z
	MOV  R30,R0
	MOV  R31,R1
	.ENDM

	.MACRO __GETB2SX
	MOV  R26,R28
	MOV  R27,R29
	SUBI R26,LOW(-@0)
	SBCI R27,HIGH(-@0)
	LD   R26,X
	.ENDM

	.MACRO __GETW2SX
	MOV  R26,R28
	MOV  R27,R29
	SUBI R26,LOW(-@0)
	SBCI R27,HIGH(-@0)
	LD   R0,X+
	LD   R27,X
	MOV  R26,R0
	.ENDM

	.MACRO __GETD2SX
	MOV  R26,R28
	MOV  R27,R29
	SUBI R26,LOW(-@0)
	SBCI R27,HIGH(-@0)
	LD   R0,X+
	LD   R1,X+
	LD   R24,X+
	LD   R25,X
	MOV  R26,R0
	MOV  R27,R1
	.ENDM

	.MACRO __GETBRSX
	MOV  R30,R28
	MOV  R31,R29
	SUBI R30,LOW(-@1)
	SBCI R31,HIGH(-@1)
	LD   R@0,Z
	.ENDM

	.MACRO __GETWRSX
	MOV  R30,R28
	MOV  R31,R29
	SUBI R30,LOW(-@2)
	SBCI R31,HIGH(-@2)
	LD   R@0,Z+
	LD   R@1,Z
	.ENDM

	.MACRO __LSLW8SX
	MOV  R30,R28
	MOV  R31,R29
	SUBI R30,LOW(-@0)
	SBCI R31,HIGH(-@0)
	LD   R31,Z
	CLR  R30
	.ENDM

	.MACRO __PUTB1SX
	MOV  R26,R28
	MOV  R27,R29
	SUBI R26,LOW(-@0)
	SBCI R27,HIGH(-@0)
	ST   X,R30
	.ENDM

	.MACRO __PUTW1SX
	MOV  R26,R28
	MOV  R27,R29
	SUBI R26,LOW(-@0)
	SBCI R27,HIGH(-@0)
	ST   X+,R30
	ST   X,R31
	.ENDM

	.MACRO __PUTD1SX
	MOV  R26,R28
	MOV  R27,R29
	SUBI R26,LOW(-@0)
	SBCI R27,HIGH(-@0)
	ST   X+,R30
	ST   X+,R31
	ST   X+,R22
	ST   X,R23
	.ENDM

	.MACRO __CLRW1SX
	MOV  R30,R28
	MOV  R31,R29
	SUBI R30,LOW(-@0)
	SBCI R31,HIGH(-@0)
	CLR  R0
	ST   Z+,R0
	ST   Z,R0
	.ENDM

	.MACRO __CLRD1SX
	MOV  R30,R28
	MOV  R31,R29
	SUBI R30,LOW(-@0)
	SBCI R31,HIGH(-@0)
	CLR  R0
	ST   Z+,R0
	ST   Z+,R0
	ST   Z+,R0
	ST   Z,R0
	.ENDM

	.MACRO __PUTB2SX
	MOV  R30,R28
	MOV  R31,R29
	SUBI R30,LOW(-@0)
	SBCI R31,HIGH(-@0)
	ST   Z,R26
	.ENDM

	.MACRO __PUTW2SX
	MOV  R30,R28
	MOV  R31,R29
	SUBI R30,LOW(-@0)
	SBCI R31,HIGH(-@0)
	ST   Z+,R26
	ST   Z,R27
	.ENDM

	.MACRO __PUTBSRX
	MOV  R30,R28
	MOV  R31,R29
	SUBI R30,LOW(-@0)
	SBCI R31,HIGH(-@0)
	ST   Z,R@1
	.ENDM

	.MACRO __PUTWSRX
	MOV  R30,R28
	MOV  R31,R29
	SUBI R30,LOW(-@2)
	SBCI R31,HIGH(-@2)
	ST   Z+,R@0
	ST   Z,R@1
	.ENDM

	.MACRO __PUTB1SNX
	MOV  R26,R28
	MOV  R27,R29
	SUBI R26,LOW(-@0)
	SBCI R27,HIGH(-@0)
	LD   R0,X+
	LD   R27,X
	MOV  R26,R0
	SUBI R26,LOW(-@1)
	SBCI R27,HIGH(-@1)
	ST   X,R30
	.ENDM

	.MACRO __PUTW1SNX
	MOV  R26,R28
	MOV  R27,R29
	SUBI R26,LOW(-@0)
	SBCI R27,HIGH(-@0)
	LD   R0,X+
	LD   R27,X
	MOV  R26,R0
	SUBI R26,LOW(-@1)
	SBCI R27,HIGH(-@1)
	ST   X+,R30
	ST   X,R31
	.ENDM

	.MACRO __PUTD1SNX
	MOV  R26,R28
	MOV  R27,R29
	SUBI R26,LOW(-@0)
	SBCI R27,HIGH(-@0)
	LD   R0,X+
	LD   R27,X
	MOV  R26,R0
	SUBI R26,LOW(-@1)
	SBCI R27,HIGH(-@1)
	ST   X+,R30
	ST   X+,R31
	ST   X+,R22
	ST   X,R23
	.ENDM

	.CSEG
	.ORG 0

	.INCLUDE "testrc5.vec"
	.INCLUDE "testrc5.inc"

__RESET:
	CLI
	CLR  R30
	OUT  EECR,R30
	OUT  MCUCR,R30

;DISABLE WATCHDOG
	LDI  R31,0x18
	OUT  WDTCR,R31
	LDI  R31,0x10
	OUT  WDTCR,R31

;CLEAR R2-R14
	LDI  R24,13
	LDI  R26,2
	CLR  R27
__CLEAR_REG:
	ST   X+,R30
	DEC  R24
	BRNE __CLEAR_REG

;CLEAR SRAM
	LDI  R24,LOW(0x200)
	LDI  R25,HIGH(0x200)
	LDI  R26,0x60
__CLEAR_SRAM:
	ST   X+,R30
	SBIW R24,1
	BRNE __CLEAR_SRAM

;GLOBAL VARIABLES INITIALIZATION
	LDI  R30,LOW(__GLOBAL_INI_TBL*2)
	LDI  R31,HIGH(__GLOBAL_INI_TBL*2)
__GLOBAL_INI_NEXT:
	LPM
	ADIW R30,1
	MOV  R1,R0
	LPM
	ADIW R30,1
	MOV  R22,R30
	MOV  R23,R31
	MOV  R31,R0
	MOV  R30,R1
	SBIW R30,0
	BREQ __GLOBAL_INI_END
	LPM
	ADIW R30,1
	MOV  R26,R0
	LPM
	ADIW R30,1
	MOV  R27,R0
	LPM
	ADIW R30,1
	MOV  R24,R0
	LPM
	ADIW R30,1
	MOV  R25,R0
__GLOBAL_INI_LOOP:
	LPM
	ADIW R30,1
	ST   X+,R0
	SBIW R24,1
	BRNE __GLOBAL_INI_LOOP
	MOV  R30,R22
	MOV  R31,R23
	RJMP __GLOBAL_INI_NEXT
__GLOBAL_INI_END:

;STACK POINTER INITIALIZATION
	LDI  R30,LOW(0x25F)
	OUT  SPL,R30
	LDI  R30,HIGH(0x25F)
	OUT  SPH,R30

;DATA STACK POINTER INITIALIZATION
	LDI  R28,LOW(0xE0)
	LDI  R29,HIGH(0xE0)

	RJMP _main

	.ESEG
	.ORG 0

	.DSEG
	.ORG 0xE0
;       1 /*********************************************
;       2 This program was produced by the
;       3 CodeWizardAVR V1.24.0 Standard
;       4 Automatic Program Generator
;       5 © Copyright 1998-2003 HP InfoTech s.r.l.
;       6 http://www.hpinfotech.ro
;       7 e-mail:office@hpinfotech.ro
;       8 
;       9 Project : Décodage d'une trame RC5 
;      10 Version : 0 . 2
;      11 Date    : 14/07/2006
;      12 Author  : Philippe Mariano                
;      13 Company : LYCEE Pierre Emile MARTIN       
;      14 Comments: 
;      15 
;      16 
;      17 Chip type           : AT90S8535
;      18 Clock frequency     : 4,000000 MHz
;      19 Memory model        : Small
;      20 External SRAM size  : 0
;      21 Data Stack size     : 128
;      22 *********************************************/
;      23 
;      24 #include <90s8535.h>
;      25 #include <stdlib.h>	// contient itoa()
;      26 #include <RC5.h>        // Contient les routines d'interruptions (réception trame RC5)
;      27 
;      28 // Alphanumeric LCD Module functions
;      29 #asm
;      30    .equ __lcd_port=0x15
   .equ __lcd_port=0x15
;      31 #endasm

;      32 #include <lcd.h> 
;      33 
;      34 
;      35 // Declare your global variables here
;      36 //------------------------------------------------------------------------------------
;      37 // Type			Nom			Rôle
;      38 // -----------------------------------------------------------------------------------
;      39 unsigned int 	g_Trame = 0;             // Contient les 14 bits de la trame RC5 à la fin
;      40 					 // de la routine de réception (contenue dans RC5.lib)
;      41 unsigned int 	g_Caractere = CONSOMME;  // drapeau indiquant la réception d'une trame 
;      42                                          // et sa consommation par la tâche de fond
;      43 
;      44 //-----------------------------------------------------------------------------------
;      45 // Programme principal
;      46 // ----------------------------------------------------------------------------------
;      47 void main(void)
;      48 {

	.CSEG
_main:
;      49 // Declare your local variables here
;      50 unsigned int Aff_int;
;      51 unsigned char *Aff_char;
;      52 
;      53 // Input/Output Ports initialization
;      54 // Port A initialization
;      55  PORTA=0x00;
	SBIW R28,2
;	Aff_int -> R16,R17
;	*Aff_char -> Y+0
	CLR  R30
	OUT  0x1B,R30
;      56 DDRA=0x00;
	OUT  0x1A,R30
;      57 
;      58 // Port B initialization
;      59 PORTB=0x00;
	OUT  0x18,R30
;      60 DDRB=0x1f;
	LDI  R30,LOW(31)
	OUT  0x17,R30
;      61 
;      62 // Port C initialization
;      63 PORTC=0x00;
	CLR  R30
	OUT  0x15,R30
;      64 DDRC=0x08;
	LDI  R30,LOW(8)
	OUT  0x14,R30
;      65 
;      66 // Port D initialization
;      67 PORTD=0x00;
	CLR  R30
	OUT  0x12,R30
;      68 DDRD=0x00;
	OUT  0x11,R30
;      69 
;      70 // Timer/Counter 0 initialization
;      71 // Clock source: System Clock
;      72 // Clock value: Timer 0 Stopped
;      73 TCCR0=0x00;
	OUT  0x33,R30
;      74 TCNT0=0x00;
	OUT  0x32,R30
;      75 
;      76 // Timer/Counter 1 initialization
;      77 // Clock source: System Clock
;      78 // Clock value: 4000,000 kHz
;      79 // Mode: Normal top=FFFFh
;      80 // OC1A output: Discon.
;      81 // OC1B output: Discon.
;      82 // Noise Canceler: On
;      83 // Input Capture on Falling Edge
;      84 TCCR1A=0x00;
	OUT  0x2F,R30
;      85 TCCR1B=0x81;
	LDI  R30,LOW(129)
	OUT  0x2E,R30
;      86 TCNT1H=0x00;
	CLR  R30
	OUT  0x2D,R30
;      87 TCNT1L=0x00;
	OUT  0x2C,R30
;      88 OCR1AH=0x00;
	OUT  0x2B,R30
;      89 OCR1AL=0x00;
	OUT  0x2A,R30
;      90 OCR1BH=0x00;
	OUT  0x29,R30
;      91 OCR1BL=0x00;
	OUT  0x28,R30
;      92 
;      93 // Timer/Counter 2 initialization
;      94 // Clock source: System Clock
;      95 // Clock value: Timer 2 Stopped
;      96 // Mode: Normal top=FFh
;      97 // OC2 output: Disconnected
;      98 ASSR=0x00;
	OUT  0x22,R30
;      99 TCCR2=0x00;
	OUT  0x25,R30
;     100 TCNT2=0x00;
	OUT  0x24,R30
;     101 OCR2=0x00;
	OUT  0x23,R30
;     102 
;     103 // External Interrupt(s) initialization
;     104 // INT0: Off
;     105 // INT1: Off
;     106 GIMSK=0x00;
	OUT  0x3B,R30
;     107 MCUCR=0x00;
	OUT  0x35,R30
;     108 
;     109 // Timer(s)/Counter(s) Interrupt(s) initialization
;     110 TIMSK=0x24; // Interrupion lors d'une capture ou si débordement
	RCALL SUBOPT_0x0
;     111 
;     112 
;     113 // LCD module initialization
;     114 lcd_init(16);
	LDI  R30,LOW(16)
	ST   -Y,R30
	RCALL _lcd_init
;     115 
;     116 // Global enable interrupts
;     117 #asm("sei")
	sei
;     118 
;     119 
;     120 while (1)
_0x1B:
;     121   {
;     122       while (g_Caractere != RECU);
_0x1E:
	LDI  R30,LOW(1)
	LDI  R31,HIGH(1)
	CP   R30,R6
	CPC  R31,R7
	BRNE _0x1E
;     123       //lcd_clear();
;     124       Aff_int = (g_Trame & 0b0011100000000000);
	__GETW1R 4,5
	ANDI R30,LOW(0x3800)
	ANDI R31,HIGH(0x3800)
	RCALL SUBOPT_0x1
;     125       Aff_int = Aff_int >> 11; 
	LDI  R30,LOW(11)
	RCALL SUBOPT_0x2
;     126       itoa(Aff_int,Aff_char);
;     127       lcd_puts(Aff_char);
;     128       Aff_int = (g_Trame & 0b0000011111000000);
	ANDI R30,LOW(0x7C0)
	ANDI R31,HIGH(0x7C0)
	RCALL SUBOPT_0x1
;     129       Aff_int = Aff_int >> 6; 
	LDI  R30,LOW(6)
	RCALL SUBOPT_0x2
;     130       itoa(Aff_int,Aff_char);
;     131       lcd_puts(Aff_char);
;     132       Aff_int = (g_Trame & 0x003f);
	ANDI R30,LOW(0x3F)
	ANDI R31,HIGH(0x3F)
	__PUTW1R 16,17
;     133       itoa(Aff_int,Aff_char);
	ST   -Y,R17
	ST   -Y,R16
	LDD  R30,Y+2
	LDD  R31,Y+2+1
	ST   -Y,R31
	ST   -Y,R30
	RCALL _itoa
;     134       lcd_puts(Aff_char);
	LD   R30,Y
	LDD  R31,Y+1
	ST   -Y,R31
	ST   -Y,R30
	RCALL _lcd_puts
;     135       
;     136       switch (g_Trame & 0b0000011111111111)
	__GETW1R 4,5
	ANDI R31,HIGH(0x7FF)
;     137       {
;     138       case 0b0000000101000010:  PORTC.3 = 1; break;
	CPI  R30,LOW(0x142)
	LDI  R26,HIGH(0x142)
	CPC  R31,R26
	BRNE _0x24
	SBI  0x15,3
	RJMP _0x23
;     139       case 0b0000000101001000:  PORTC.3 = 0; break; 
_0x24:
	CPI  R30,LOW(0x148)
	LDI  R26,HIGH(0x148)
	CPC  R31,R26
	BRNE _0x23
	CBI  0x15,3
;     140       };
_0x23:
;     141       
;     142       g_Caractere = CONSOMME;
	CLR  R6
	CLR  R7
;     143       
;     144   };
	RJMP _0x1B
;     145 }
	ADIW R28,2
_0x26:
	RJMP _0x26

	.DSEG

	.CSEG
_timer1_capt_isr:
	RCALL __SAVEISR
	MOV  R30,R8
	CPI  R30,0
	BRNE _0x2D
	RCALL SUBOPT_0x3
	RCALL SUBOPT_0x4
	RCALL SUBOPT_0x5
	RJMP _0x2C
_0x2D:
	CPI  R30,LOW(0x1)
	BRNE _0x2E
	RCALL SUBOPT_0x6
	BRSH _0x30
	RCALL SUBOPT_0x7
	BRLO _0x31
_0x30:
	RJMP _0x2F
_0x31:
	LDI  R30,LOW(2)
	MOV  R8,R30
	RJMP _0x32
_0x2F:
	RCALL SUBOPT_0x8
	RCALL SUBOPT_0x9
	BRSH _0x34
	RCALL SUBOPT_0xA
	BRLO _0x35
_0x34:
	RJMP _0x33
_0x35:
	RCALL SUBOPT_0xB
	RJMP _0x36
_0x33:
	RCALL SUBOPT_0xC
_0x36:
_0x32:
	RJMP _0x2C
_0x2E:
	CPI  R30,LOW(0x2)
	BRNE _0x37
	RCALL SUBOPT_0x4
	RCALL SUBOPT_0x8
	RCALL SUBOPT_0xD
	BRSH _0x39
	RCALL SUBOPT_0x7
	BRLO _0x3A
_0x39:
	RJMP _0x38
_0x3A:
	RCALL SUBOPT_0x5
	RCALL SUBOPT_0x3
	RJMP _0x3B
_0x38:
	RCALL SUBOPT_0xC
_0x3B:
	RJMP _0x2C
_0x37:
	CPI  R30,LOW(0x3)
	BRNE _0x3C
	RCALL SUBOPT_0x4
	RCALL SUBOPT_0x8
	RCALL SUBOPT_0xD
	BRSH _0x3E
	RCALL SUBOPT_0x7
	BRLO _0x3F
_0x3E:
	RJMP _0x3D
_0x3F:
	LDI  R30,LOW(4)
	MOV  R8,R30
	RJMP _0x40
_0x3D:
	RCALL SUBOPT_0x8
	RCALL SUBOPT_0x9
	BRSH _0x42
	RCALL SUBOPT_0xA
	BRLO _0x43
_0x42:
	RJMP _0x41
_0x43:
	RCALL SUBOPT_0x5
	RCALL SUBOPT_0x3
	RJMP _0x44
_0x41:
	RCALL SUBOPT_0xC
_0x44:
_0x40:
	RJMP _0x2C
_0x3C:
	CPI  R30,LOW(0x4)
	BRNE _0x2C
	RCALL SUBOPT_0x6
	BRSH _0x47
	RCALL SUBOPT_0x7
	BRLO _0x48
_0x47:
	RJMP _0x46
_0x48:
	RCALL SUBOPT_0xB
	RJMP _0x49
_0x46:
	RCALL SUBOPT_0xC
_0x49:
_0x2C:
	TST  R9
	BRNE _0x4A
	RCALL SUBOPT_0xE
	LDI  R30,LOW(1)
	LDI  R31,HIGH(1)
	__PUTW1R 6,7
_0x4A:
	RCALL SUBOPT_0xF
	RCALL __LOADISR
	RETI
_timer1_ovf_isr:
	RCALL __SAVEISR
	RCALL SUBOPT_0xE
	RCALL SUBOPT_0xF
	RCALL SUBOPT_0x0
	RCALL __LOADISR
	RETI
    .equ __lcd_direction=__lcd_port-1
    .equ __lcd_pin=__lcd_port-2
    .equ __lcd_rs=0
    .equ __lcd_rd=1
    .equ __lcd_enable=2
    .equ __lcd_busy_flag=7

	.DSEG
__base_y_G4:
	.BYTE 0x4

	.CSEG
__lcd_ready:
    in    r26,__lcd_direction
    andi  r26,0xf                 ;set as input
    out   __lcd_direction,r26
    sbi   __lcd_port,__lcd_rd     ;RD=1
    cbi   __lcd_port,__lcd_rs     ;RS=0
__lcd_busy:
    rcall __lcd_delay
    sbi   __lcd_port,__lcd_enable ;EN=1
    rcall __lcd_delay
    in    r26,__lcd_pin
    cbi   __lcd_port,__lcd_enable ;EN=0
    rcall __lcd_delay
    sbi   __lcd_port,__lcd_enable ;EN=1
    rcall __lcd_delay
    cbi   __lcd_port,__lcd_enable ;EN=0
    sbrc  r26,__lcd_busy_flag
    rjmp  __lcd_busy
	RET
__lcd_write_nibble:
    andi  r26,0xf0
    or    r26,r27
    out   __lcd_port,r26          ;write
    sbi   __lcd_port,__lcd_enable ;EN=1
    rcall __lcd_delay
    cbi   __lcd_port,__lcd_enable ;EN=0
__lcd_delay:
    ldi   r31,15
__lcd_delay0:
    dec   r31
    brne  __lcd_delay0
    ret
__lcd_write_data:
    cbi  __lcd_port,__lcd_rd 	  ;RD=0
    in    r26,__lcd_direction
    ori   r26,0xf7                ;set as output
    out   __lcd_direction,r26
    in    r27,__lcd_port
    andi  r27,0xf
    ld    r26,y
    rcall __lcd_write_nibble      ;RD=0, write MSN
    ld    r26,y
    swap  r26
    rcall __lcd_write_nibble      ;write LSN
    sbi   __lcd_port,__lcd_rd     ;RD=1
	ADIW R28,1
	RET
__lcd_read_nibble:
    sbi   __lcd_port,__lcd_enable ;EN=1
    rcall __lcd_delay
    in    r30,__lcd_pin           ;read
    cbi   __lcd_port,__lcd_enable ;EN=0
    rcall __lcd_delay
    andi  r30,0xf0
    ret
_lcd_read_byte0_G4:
    rcall __lcd_delay
    rcall __lcd_read_nibble       ;read MSN
    mov   r26,r30
    rcall __lcd_read_nibble       ;read LSN
    cbi   __lcd_port,__lcd_rd     ;RD=0
    swap  r30
    or    r30,r26
	RET
_lcd_gotoxy:
	RCALL __lcd_ready
	LD   R30,Y
	CLR  R31
	SUBI R30,LOW(-__base_y_G4)
	SBCI R31,HIGH(-__base_y_G4)
	LD   R30,Z
	LDD  R26,Y+1
	ADD  R30,R26
	RCALL SUBOPT_0x10
	LDD  R10,Y+1
	LDD  R11,Y+0
	ADIW R28,2
	RET
_lcd_clear:
	RCALL __lcd_ready
	LDI  R30,LOW(2)
	RCALL SUBOPT_0x10
	RCALL __lcd_ready
	LDI  R30,LOW(12)
	RCALL SUBOPT_0x10
	RCALL __lcd_ready
	LDI  R30,LOW(1)
	RCALL SUBOPT_0x10
	CLR  R30
	MOV  R11,R30
	MOV  R10,R30
	RET
_lcd_putchar:
    push r30
    push r31
    ld   r26,y
    set
    cpi  r26,10
    breq __lcd_putchar1
    clt
	INC  R10
	CP   R12,R10
	BRSH _0x52
	__lcd_putchar1:
	INC  R11
	CLR  R30
	ST   -Y,R30
	ST   -Y,R11
	RCALL _lcd_gotoxy
	brts __lcd_putchar0
_0x52:
    rcall __lcd_ready
    sbi  __lcd_port,__lcd_rs ;RS=1
    ld   r26,y
    st   -y,r26
    rcall __lcd_write_data
__lcd_putchar0:
    pop  r31
    pop  r30
	ADIW R28,1
	RET
_lcd_puts:
    ldd  r31,y+1
    ld   r30,y
__lcd_puts0:
    ld   r26,z+
    tst  r26
    breq __lcd_puts1
    st   -y,r26    
    rcall _lcd_putchar
    rjmp __lcd_puts0
__lcd_puts1:
	ADIW R28,2
	RET
__long_delay_G4:
    clr   r26
    clr   r27
__long_delay0:
    sbiw  r26,1         ;2 cycles
    brne  __long_delay0 ;2 cycles
	RET
__lcd_init_write_G4:
    cbi  __lcd_port,__lcd_rd 	  ;RD=0
    in    r26,__lcd_direction
    ori   r26,0xf7                ;set as output
    out   __lcd_direction,r26
    in    r27,__lcd_port
    andi  r27,0xf
    ld    r26,y
    rcall __lcd_write_nibble      ;RD=0, write MSN
    sbi   __lcd_port,__lcd_rd     ;RD=1
	ADIW R28,1
	RET
_lcd_init:
    cbi   __lcd_port,__lcd_enable ;EN=0
    cbi   __lcd_port,__lcd_rs     ;RS=0
	LDD  R12,Y+0
	LD   R30,Y
	SUBI R30,-LOW(128)
	__PUTB1MN __base_y_G4,2
	LD   R30,Y
	SUBI R30,-LOW(192)
	__PUTB1MN __base_y_G4,3
	RCALL SUBOPT_0x11
	RCALL SUBOPT_0x11
	RCALL SUBOPT_0x11
	RCALL __long_delay_G4
	LDI  R30,LOW(32)
	ST   -Y,R30
	RCALL __lcd_init_write_G4
	RCALL __long_delay_G4
	LDI  R30,LOW(40)
	RCALL SUBOPT_0x10
	RCALL __long_delay_G4
	LDI  R30,LOW(4)
	RCALL SUBOPT_0x10
	RCALL __long_delay_G4
	LDI  R30,LOW(133)
	RCALL SUBOPT_0x10
	RCALL __long_delay_G4
    in    r26,__lcd_direction
    andi  r26,0xf                 ;set as input
    out   __lcd_direction,r26
    sbi   __lcd_port,__lcd_rd     ;RD=1
	RCALL _lcd_read_byte0_G4
	CPI  R30,LOW(0x5)
	BREQ _0x57
	CLR  R30
	RJMP _0x58
_0x57:
	RCALL __lcd_ready
	LDI  R30,LOW(6)
	RCALL SUBOPT_0x10
	RCALL _lcd_clear
	LDI  R30,LOW(1)
_0x58:
	ADIW R28,1
	RET

;OPTIMIZER ADDED SUBROUTINE, CALLED 2 TIMES
SUBOPT_0x0:
	LDI  R30,LOW(36)
	OUT  0x39,R30
	RET

;OPTIMIZER ADDED SUBROUTINE, CALLED 2 TIMES
SUBOPT_0x1:
	__PUTW1R 16,17
	__GETW2R 16,17
	RET

;OPTIMIZER ADDED SUBROUTINE, CALLED 2 TIMES
SUBOPT_0x2:
	RCALL __LSRW12
	__PUTW1R 16,17
	ST   -Y,R17
	ST   -Y,R16
	LDD  R30,Y+2
	LDD  R31,Y+2+1
	ST   -Y,R31
	ST   -Y,R30
	RCALL _itoa
	LD   R30,Y
	LDD  R31,Y+1
	ST   -Y,R31
	ST   -Y,R30
	RCALL _lcd_puts
	__GETW1R 4,5
	RET

;OPTIMIZER ADDED SUBROUTINE, CALLED 3 TIMES
SUBOPT_0x3:
	LDI  R30,LOW(1)
	MOV  R8,R30
	RET

;OPTIMIZER ADDED SUBROUTINE, CALLED 3 TIMES
SUBOPT_0x4:
	LDI  R30,LOW(65)
	OUT  0x2E,R30
	RET

;OPTIMIZER ADDED SUBROUTINE, CALLED 3 TIMES
SUBOPT_0x5:
	__GETW1R 4,5
	LSL  R30
	ROL  R31
	ORI  R30,1
	__PUTW1R 4,5
	DEC  R9
	RET

;OPTIMIZER ADDED SUBROUTINE, CALLED 2 TIMES
SUBOPT_0x6:
	LDI  R30,LOW(1)
	OUT  0x2E,R30
	IN   R30,0x26
	IN   R31,0x26+1
	MOV  R26,R30
	MOV  R27,R31
	LDI  R30,LOW(2400)
	LDI  R31,HIGH(2400)
	CP   R30,R26
	CPC  R31,R27
	RET

;OPTIMIZER ADDED SUBROUTINE, CALLED 4 TIMES
SUBOPT_0x7:
	IN   R30,0x26
	IN   R31,0x26+1
	CPI  R30,LOW(0x12C0)
	LDI  R26,HIGH(0x12C0)
	CPC  R31,R26
	RET

;OPTIMIZER ADDED SUBROUTINE, CALLED 4 TIMES
SUBOPT_0x8:
	IN   R30,0x26
	IN   R31,0x26+1
	MOV  R26,R30
	MOV  R27,R31
	RET

;OPTIMIZER ADDED SUBROUTINE, CALLED 2 TIMES
SUBOPT_0x9:
	LDI  R30,LOW(6400)
	LDI  R31,HIGH(6400)
	CP   R30,R26
	CPC  R31,R27
	RET

;OPTIMIZER ADDED SUBROUTINE, CALLED 2 TIMES
SUBOPT_0xA:
	IN   R30,0x26
	IN   R31,0x26+1
	CPI  R30,LOW(0x1F40)
	LDI  R26,HIGH(0x1F40)
	CPC  R31,R26
	RET

;OPTIMIZER ADDED SUBROUTINE, CALLED 2 TIMES
SUBOPT_0xB:
	LSL  R4
	ROL  R5
	DEC  R9
	LDI  R30,LOW(3)
	MOV  R8,R30
	RET

;OPTIMIZER ADDED SUBROUTINE, CALLED 4 TIMES
SUBOPT_0xC:
	LDI  R30,LOW(4)
	OUT  0x39,R30
	RET

;OPTIMIZER ADDED SUBROUTINE, CALLED 2 TIMES
SUBOPT_0xD:
	LDI  R30,LOW(2400)
	LDI  R31,HIGH(2400)
	CP   R30,R26
	CPC  R31,R27
	RET

;OPTIMIZER ADDED SUBROUTINE, CALLED 2 TIMES
SUBOPT_0xE:
	CLR  R8
	LDI  R30,LOW(14)
	MOV  R9,R30
	LDI  R30,LOW(1)
	OUT  0x2E,R30
	RET

;OPTIMIZER ADDED SUBROUTINE, CALLED 2 TIMES
SUBOPT_0xF:
	CLR  R30
	CLR  R31
	OUT  0x2C+1,R31
	OUT  0x2C,R30
	RET

;OPTIMIZER ADDED SUBROUTINE, CALLED 8 TIMES
SUBOPT_0x10:
	ST   -Y,R30
	RJMP __lcd_write_data

;OPTIMIZER ADDED SUBROUTINE, CALLED 3 TIMES
SUBOPT_0x11:
	RCALL __long_delay_G4
	LDI  R30,LOW(48)
	ST   -Y,R30
	RJMP __lcd_init_write_G4

_itoa:
	ld   r26,y+
	ld   r27,y+
	ld   r30,y+
	ld   r31,y+
	adiw r30,0
	brpl __itoa0
	com  r30
	com  r31
	adiw r30,1
	ldi  r22,'-'
	st   x+,r22
__itoa0:
	clt
	ldi  r24,low(10000)
	ldi  r25,high(10000)
	rcall __itoa1
	ldi  r24,low(1000)
	ldi  r25,high(1000)
	rcall __itoa1
	ldi  r24,100
	clr  r25
	rcall __itoa1
	ldi  r24,10
	rcall __itoa1
	mov  r22,r30
	rcall __itoa5
	clr  r22
	st   x,r22
	ret
__itoa1:
	clr	 r22
__itoa2:
	cp   r30,r24
	cpc  r31,r25
	brlo __itoa3
	inc  r22
	sub  r30,r24
	sbc  r31,r25
	brne __itoa2
__itoa3:
	tst  r22
	brne __itoa4
	brts __itoa5
	ret
__itoa4:
	set
__itoa5:
	subi r22,-0x30
	st   x+,r22
	ret

__SAVEISR:
	ST   -Y,R0
	ST   -Y,R1
	ST   -Y,R15
	ST   -Y,R22
	ST   -Y,R23
	ST   -Y,R24
	ST   -Y,R25
	ST   -Y,R26
	ST   -Y,R27
	ST   -Y,R30
	ST   -Y,R31
	IN   R0,SREG
	ST   -Y,R0
	RET

__LOADISR:
	LD   R0,Y+
	OUT  SREG,R0
	LD   R31,Y+
	LD   R30,Y+
	LD   R27,Y+
	LD   R26,Y+
	LD   R25,Y+
	LD   R24,Y+
	LD   R23,Y+
	LD   R22,Y+
	LD   R15,Y+
	LD   R1,Y+
	LD   R0,Y+
	RET

__LSRW12:
	TST  R30
	MOV  R0,R30
	MOV  R30,R26
	MOV  R31,R27
	BREQ __LSRW12R
__LSRW12L:
	LSR  R31
	ROR  R30
	DEC  R0
	BRNE __LSRW12L
__LSRW12R:
	RET

