;CodeVisionAVR C Compiler V1.0.2.2d Standard
;(C) Copyright 1998-2002 Pavel Haiduc, HP InfoTech s.r.l.
;http://www.hpinfotech.ro
;e-mail:office@hpinfotech.ro , hpinfotech@xmail.ro

;Chip type           : AT90S8535
;Clock frequency     : 4,000000 MHz
;Memory model        : Small
;Optimize for        : Size
;Internal SRAM size  : 512
;External SRAM size  : 0
;Data Stack size     : 128
;Promote char to int : No
;char is unsigned    : Yes
;Automatic register allocation : On
;Use AVR Studio Terminal I/O   : No

	.DEVICE AT90S8535
	.LISTMAC
	.EQU UDRE=0x5
	.EQU RXC=0x7
	.EQU USR=0xB
	.EQU UDR=0xC
	.EQU EERE=0x0
	.EQU EEWE=0x1
	.EQU EEMWE=0x2
	.EQU SPSR=0xE
	.EQU SPDR=0xF
	.EQU EECR=0x1C
	.EQU EEDR=0x1D
	.EQU EEARL=0x1E
	.EQU EEARH=0x1F
	.EQU WDTCR=0x21
	.EQU MCUCR=0x35
	.EQU RAMPZ=0x3B
	.EQU SPL=0x3D
	.EQU SPH=0x3E
	.EQU SREG=0x3F
	.DEF R0X0=R0
	.DEF R0X1=R1
	.DEF R0X2=R2
	.DEF R0X3=R3
	.DEF R0X4=R4
	.DEF R0X5=R5
	.DEF R0X6=R6
	.DEF R0X7=R7
	.DEF R0X8=R8
	.DEF R0X9=R9
	.DEF R0XA=R10
	.DEF R0XB=R11
	.DEF R0XC=R12
	.DEF R0XD=R13
	.DEF R0XE=R14
	.DEF R0XF=R15
	.DEF R0X10=R16
	.DEF R0X11=R17
	.DEF R0X12=R18
	.DEF R0X13=R19
	.DEF R0X14=R20
	.DEF R0X15=R21
	.DEF R0X16=R22
	.DEF R0X17=R23
	.DEF R0X18=R24
	.DEF R0X19=R25
	.DEF R0X1A=R26
	.DEF R0X1B=R27
	.DEF R0X1C=R28
	.DEF R0X1D=R29
	.DEF R0X1E=R30
	.DEF R0X1F=R31
	.EQU __se_bit=0x40
	.EQU __sm_mask=0x30
	.EQU __sm_powerdown=0x20

	.MACRO __CPD1N
	CPI  R30,LOW(@0)
	LDI  R26,HIGH(@0)
	CPC  R31,R26
	LDI  R26,BYTE3(@0)
	CPC  R22,R26
	LDI  R26,BYTE4(@0)
	CPC  R23,R26
	.ENDM

	.MACRO __CPD2N
	CPI  R26,LOW(@0)
	LDI  R30,HIGH(@0)
	CPC  R27,R30
	LDI  R30,BYTE3(@0)
	CPC  R24,R30
	LDI  R30,BYTE4(@0)
	CPC  R25,R30
	.ENDM

	.MACRO __CPWRR
	CP   R@0,R@2
	CPC  R@1,R@3
	.ENDM

	.MACRO __CPWRN
	CPI  R@0,LOW(@2)
	LDI  R30,HIGH(@2)
	CPC  R@1,R30
	.ENDM

	.MACRO __ADDD1N
	SUBI R30,LOW(-@0)
	SBCI R31,HIGH(-@0)
	SBCI R22,BYTE3(-@0)
	SBCI R23,BYTE4(-@0)
	.ENDM

	.MACRO __ADDD2N
	SUBI R26,LOW(-@0)
	SBCI R27,HIGH(-@0)
	SBCI R24,BYTE3(-@0)
	SBCI R25,BYTE4(-@0)
	.ENDM

	.MACRO __SUBD1N
	SUBI R30,LOW(@0)
	SBCI R31,HIGH(@0)
	SBCI R22,BYTE3(@0)
	SBCI R23,BYTE4(@0)
	.ENDM

	.MACRO __SUBD2N
	SUBI R26,LOW(@0)
	SBCI R27,HIGH(@0)
	SBCI R24,BYTE3(@0)
	SBCI R25,BYTE4(@0)
	.ENDM

	.MACRO __ANDD1N
	ANDI R30,LOW(@0)
	ANDI R31,HIGH(@0)
	ANDI R22,BYTE3(@0)
	ANDI R23,BYTE4(@0)
	.ENDM

	.MACRO __ORD1N
	ORI  R30,LOW(@0)
	ORI  R31,HIGH(@0)
	ORI  R22,BYTE3(@0)
	ORI  R23,BYTE4(@0)
	.ENDM

	.MACRO __DELAY_USB
	LDI  R24,LOW(@0)
__DELAY_USB_LOOP:
	DEC  R24
	BRNE __DELAY_USB_LOOP
	.ENDM

	.MACRO __DELAY_USW
	LDI  R24,LOW(@0)
	LDI  R25,HIGH(@0)
__DELAY_USW_LOOP:
	SBIW R24,1
	BRNE __DELAY_USW_LOOP
	.ENDM

	.MACRO __CLRD1S
	CLR  R30
	STD  Y+@0,R30
	STD  Y+@0+1,R30
	STD  Y+@0+2,R30
	STD  Y+@0+3,R30
	.ENDM

	.MACRO __GETD1S
	LDD  R30,Y+@0
	LDD  R31,Y+@0+1
	LDD  R22,Y+@0+2
	LDD  R23,Y+@0+3
	.ENDM

	.MACRO __PUTD1S
	STD  Y+@0,R30
	STD  Y+@0+1,R31
	STD  Y+@0+2,R22
	STD  Y+@0+3,R23
	.ENDM

	.MACRO __POINTB1MN
	LDI  R30,LOW(@0+@1)
	.ENDM

	.MACRO __POINTW1MN
	LDI  R30,LOW(@0+@1)
	LDI  R31,HIGH(@0+@1)
	.ENDM

	.MACRO __POINTW1FN
	LDI  R30,LOW(2*@0+@1)
	LDI  R31,HIGH(2*@0+@1)
	.ENDM

	.MACRO __POINTB2MN
	LDI  R26,LOW(@0+@1)
	.ENDM

	.MACRO __POINTW2MN
	LDI  R26,LOW(@0+@1)
	LDI  R27,HIGH(@0+@1)
	.ENDM

	.MACRO __GETD1N
	LDI  R30,LOW(@0)
	LDI  R31,HIGH(@0)
	LDI  R22,BYTE3(@0)
	LDI  R23,BYTE4(@0)
	.ENDM

	.MACRO __GETD2N
	LDI  R26,LOW(@0)
	LDI  R27,HIGH(@0)
	LDI  R24,BYTE3(@0)
	LDI  R25,BYTE4(@0)
	.ENDM

	.MACRO __GETD2S
	LDD  R26,Y+@0
	LDD  R27,Y+@0+1
	LDD  R24,Y+@0+2
	LDD  R25,Y+@0+3
	.ENDM

	.MACRO __GETB1MN
	LDS  R30,@0+@1
	.ENDM

	.MACRO __GETW1MN
	LDS  R30,@0+@1
	LDS  R31,@0+@1+1
	.ENDM

	.MACRO __GETD1MN
	LDS  R30,@0+@1
	LDS  R31,@0+@1+1
	LDS  R22,@0+@1+2
	LDS  R23,@0+@1+3
	.ENDM

	.MACRO __GETBRMN
	LDS  R@2,@0+@1
	.ENDM

	.MACRO __GETWRMN
	LDS  R@2,@0+@1
	LDS  R@3,@0+@1+1
	.ENDM

	.MACRO __GETB2MN
	LDS  R26,@0+@1
	.ENDM

	.MACRO __GETW2MN
	LDS  R26,@0+@1
	LDS  R27,@0+@1+1
	.ENDM

	.MACRO __GETD2MN
	LDS  R26,@0+@1
	LDS  R27,@0+@1+1
	LDS  R24,@0+@1+2
	LDS  R25,@0+@1+3
	.ENDM

	.MACRO __PUTB1MN
	STS  @0+@1,R30
	.ENDM

	.MACRO __PUTW1MN
	STS  @0+@1,R30
	STS  @0+@1+1,R31
	.ENDM

	.MACRO __PUTD1MN
	STS  @0+@1,R30
	STS  @0+@1+1,R31
	STS  @0+@1+2,R22
	STS  @0+@1+3,R23
	.ENDM

	.MACRO __PUTBMRN
	STS  @0+@1,R@2
	.ENDM

	.MACRO __PUTWMRN
	STS  @0+@1,R@2
	STS  @0+@1+1,R@3
	.ENDM

	.MACRO __GETW1R
	MOV  R30,R@0
	MOV  R31,R@1
	.ENDM

	.MACRO __GETW2R
	MOV  R26,R@0
	MOV  R27,R@1
	.ENDM

	.MACRO __GETWRN
	LDI  R@0,LOW(@2)
	LDI  R@1,HIGH(@2)
	.ENDM

	.MACRO __PUTW1R
	MOV  R@0,R30
	MOV  R@1,R31
	.ENDM

	.MACRO __ADDWRN
	SUBI R@0,LOW(-@2)
	SBCI R@1,HIGH(-@2)
	.ENDM

	.MACRO __ADDWRR
	ADD  R@0,R@2
	ADC  R@1,R@3
	.ENDM

	.MACRO __SUBWRN
	SUBI R@0,LOW(@2)
	SBCI R@1,HIGH(@2)
	.ENDM

	.MACRO __SUBWRR
	SUB  R@0,R@2
	SBC  R@1,R@3
	.ENDM

	.MACRO __ANDWRN
	ANDI R@0,LOW(@2)
	ANDI R@1,HIGH(@2)
	.ENDM

	.MACRO __ANDWRR
	AND  R@0,R@2
	AND  R@1,R@3
	.ENDM

	.MACRO __ORWRN
	ORI  R@0,LOW(@2)
	ORI  R@1,HIGH(@2)
	.ENDM

	.MACRO __ORWRR
	OR   R@0,R@2
	OR   R@1,R@3
	.ENDM

	.MACRO __EORWRR
	EOR  R@0,R@2
	EOR  R@1,R@3
	.ENDM

	.MACRO __GETWRS
	LDD  R@0,Y+@2
	LDD  R@1,Y+@2+1
	.ENDM

	.MACRO __PUTWSR
	STD  Y+@2,R@0
	STD  Y+@2+1,R@1
	.ENDM

	.MACRO __MOVEWRR
	MOV  R@0,R@2
	MOV  R@1,R@3
	.ENDM

	.MACRO __INWR
	IN   R@0,@2
	IN   R@1,@2+1
	.ENDM

	.MACRO __OUTWR
	OUT  @2+1,R@1
	OUT  @2,R@0
	.ENDM

	.MACRO __CALL1MN
	LDS  R30,@0+@1
	LDS  R31,@0+@1+1
	ICALL
	.ENDM

	.MACRO __NBST
	BST  R@0,@1
	IN   R30,SREG
	LDI  R31,0x40
	EOR  R30,R31
	OUT  SREG,R30
	.ENDM


	.MACRO __PUTB1SN
	LDD  R26,Y+@0
	LDD  R27,Y+@0+1
	SUBI R26,LOW(-@1)
	SBCI R27,HIGH(-@1)
	ST   X,R30
	.ENDM

	.MACRO __PUTW1SN
	LDD  R26,Y+@0
	LDD  R27,Y+@0+1
	SUBI R26,LOW(-@1)
	SBCI R27,HIGH(-@1)
	ST   X+,R30
	ST   X,R31
	.ENDM

	.MACRO __PUTD1SN
	LDD  R26,Y+@0
	LDD  R27,Y+@0+1
	SUBI R26,LOW(-@1)
	SBCI R27,HIGH(-@1)
	RCALL __PUTDP1
	.ENDM

	.MACRO __PUTB1SNS
	LDD  R26,Y+@0
	LDD  R27,Y+@0+1
	ADIW R26,@1
	ST   X,R30
	.ENDM

	.MACRO __PUTW1SNS
	LDD  R26,Y+@0
	LDD  R27,Y+@0+1
	ADIW R26,@1
	ST   X+,R30
	ST   X,R31
	.ENDM

	.MACRO __PUTD1SNS
	LDD  R26,Y+@0
	LDD  R27,Y+@0+1
	ADIW R26,@1
	RCALL __PUTDP1
	.ENDM

	.MACRO __PUTB1PMN
	LDS  R26,@0
	LDS  R27,@0+1
	SUBI R26,LOW(-@1)
	SBCI R27,HIGH(-@1)
	ST   X,R30
	.ENDM

	.MACRO __PUTW1PMN
	LDS  R26,@0
	LDS  R27,@0+1
	SUBI R26,LOW(-@1)
	SBCI R27,HIGH(-@1)
	ST   X+,R30
	ST   X,R31
	.ENDM

	.MACRO __PUTD1PMN
	LDS  R26,@0
	LDS  R27,@0+1
	SUBI R26,LOW(-@1)
	SBCI R27,HIGH(-@1)
	RCALL __PUTDP1
	.ENDM

	.MACRO __PUTB1PMNS
	LDS  R26,@0
	LDS  R27,@0+1
	ADIW R26,@1
	ST   X,R30
	.ENDM

	.MACRO __PUTW1PMNS
	LDS  R26,@0
	LDS  R27,@0+1
	ADIW R26,@1
	ST   X+,R30
	ST   X,R31
	.ENDM

	.MACRO __PUTD1PMNS
	LDS  R26,@0
	LDS  R27,@0+1
	ADIW R26,@1
	RCALL __PUTDP1
	.ENDM

	.MACRO __GETB1SX
	MOV  R30,R28
	MOV  R31,R29
	SUBI R30,LOW(-@0)
	SBCI R31,HIGH(-@0)
	LD   R30,Z
	.ENDM

	.MACRO __GETW1SX
	MOV  R30,R28
	MOV  R31,R29
	SUBI R30,LOW(-@0)
	SBCI R31,HIGH(-@0)
	LD   R0,Z+
	LD   R31,Z
	MOV  R30,R0
	.ENDM

	.MACRO __GETD1SX
	MOV  R30,R28
	MOV  R31,R29
	SUBI R30,LOW(-@0)
	SBCI R31,HIGH(-@0)
	LD   R0,Z+
	LD   R1,Z+
	LD   R22,Z+
	LD   R23,Z
	MOV  R30,R0
	MOV  R31,R1
	.ENDM

	.MACRO __GETB2SX
	MOV  R26,R28
	MOV  R27,R29
	SUBI R26,LOW(-@0)
	SBCI R27,HIGH(-@0)
	LD   R26,X
	.ENDM

	.MACRO __GETW2SX
	MOV  R26,R28
	MOV  R27,R29
	SUBI R26,LOW(-@0)
	SBCI R27,HIGH(-@0)
	LD   R0,X+
	LD   R27,X
	MOV  R26,R0
	.ENDM

	.MACRO __GETD2SX
	MOV  R26,R28
	MOV  R27,R29
	SUBI R26,LOW(-@0)
	SBCI R27,HIGH(-@0)
	LD   R0,X+
	LD   R1,X+
	LD   R24,X+
	LD   R25,X
	MOV  R26,R0
	MOV  R27,R1
	.ENDM

	.MACRO __GETBRSX
	MOV  R30,R28
	MOV  R31,R29
	SUBI R30,LOW(-@1)
	SBCI R31,HIGH(-@1)
	LD   R@0,Z
	.ENDM

	.MACRO __GETWRSX
	MOV  R30,R28
	MOV  R31,R29
	SUBI R30,LOW(-@2)
	SBCI R31,HIGH(-@2)
	LD   R@0,Z+
	LD   R@1,Z
	.ENDM

	.MACRO __LSLW8SX
	MOV  R30,R28
	MOV  R31,R29
	SUBI R30,LOW(-@0)
	SBCI R31,HIGH(-@0)
	LD   R31,Z
	CLR  R30
	.ENDM

	.MACRO __PUTB1SX
	MOV  R26,R28
	MOV  R27,R29
	SUBI R26,LOW(-@0)
	SBCI R27,HIGH(-@0)
	ST   X,R30
	.ENDM

	.MACRO __PUTW1SX
	MOV  R26,R28
	MOV  R27,R29
	SUBI R26,LOW(-@0)
	SBCI R27,HIGH(-@0)
	ST   X+,R30
	ST   X,R31
	.ENDM

	.MACRO __PUTD1SX
	MOV  R26,R28
	MOV  R27,R29
	SUBI R26,LOW(-@0)
	SBCI R27,HIGH(-@0)
	ST   X+,R30
	ST   X+,R31
	ST   X+,R22
	ST   X,R23
	.ENDM

	.MACRO __CLRW1SX
	MOV  R30,R28
	MOV  R31,R29
	SUBI R30,LOW(-@0)
	SBCI R31,HIGH(-@0)
	CLR  R0
	ST   Z+,R0
	ST   Z,R0
	.ENDM

	.MACRO __CLRD1SX
	MOV  R30,R28
	MOV  R31,R29
	SUBI R30,LOW(-@0)
	SBCI R31,HIGH(-@0)
	CLR  R0
	ST   Z+,R0
	ST   Z+,R0
	ST   Z+,R0
	ST   Z,R0
	.ENDM

	.MACRO __PUTB2SX
	MOV  R30,R28
	MOV  R31,R29
	SUBI R30,LOW(-@0)
	SBCI R31,HIGH(-@0)
	ST   Z,R26
	.ENDM

	.MACRO __PUTW2SX
	MOV  R30,R28
	MOV  R31,R29
	SUBI R30,LOW(-@0)
	SBCI R31,HIGH(-@0)
	ST   Z+,R26
	ST   Z,R27
	.ENDM

	.MACRO __PUTBSRX
	MOV  R30,R28
	MOV  R31,R29
	SUBI R30,LOW(-@0)
	SBCI R31,HIGH(-@0)
	ST   Z,R@1
	.ENDM

	.MACRO __PUTWSRX
	MOV  R30,R28
	MOV  R31,R29
	SUBI R30,LOW(-@2)
	SBCI R31,HIGH(-@2)
	ST   Z+,R@0
	ST   Z,R@1
	.ENDM

	.MACRO __PUTB1SNX
	MOV  R26,R28
	MOV  R27,R29
	SUBI R26,LOW(-@0)
	SBCI R27,HIGH(-@0)
	LD   R0,X+
	LD   R27,X
	MOV  R26,R0
	SUBI R26,LOW(-@1)
	SBCI R27,HIGH(-@1)
	ST   X,R30
	.ENDM

	.MACRO __PUTW1SNX
	MOV  R26,R28
	MOV  R27,R29
	SUBI R26,LOW(-@0)
	SBCI R27,HIGH(-@0)
	LD   R0,X+
	LD   R27,X
	MOV  R26,R0
	SUBI R26,LOW(-@1)
	SBCI R27,HIGH(-@1)
	ST   X+,R30
	ST   X,R31
	.ENDM

	.MACRO __PUTD1SNX
	MOV  R26,R28
	MOV  R27,R29
	SUBI R26,LOW(-@0)
	SBCI R27,HIGH(-@0)
	LD   R0,X+
	LD   R27,X
	MOV  R26,R0
	SUBI R26,LOW(-@1)
	SBCI R27,HIGH(-@1)
	ST   X+,R30
	ST   X+,R31
	ST   X+,R22
	ST   X,R23
	.ENDM

	.CSEG
	.ORG 0x11

	.INCLUDE "essai1.inc"

__RESET:
	CLI
	CLR  R30
	OUT  EECR,R30
	OUT  MCUCR,R30

;DISABLE WATCHDOG
	LDI  R31,0x18
	OUT  WDTCR,R31
	LDI  R31,0x10
	OUT  WDTCR,R31

;CLEAR R2-R15
	LDI  R24,14
	LDI  R26,2
	CLR  R27
__CLEAR_REG:
	ST   X+,R30
	DEC  R24
	BRNE __CLEAR_REG

;CLEAR SRAM
	LDI  R24,LOW(0x200)
	LDI  R25,HIGH(0x200)
	LDI  R26,0x60
__CLEAR_SRAM:
	ST   X+,R30
	SBIW R24,1
	BRNE __CLEAR_SRAM

;GLOBAL VARIABLES INITIALIZATION
	LDI  R30,LOW(__GLOBAL_INI_TBL*2)
	LDI  R31,HIGH(__GLOBAL_INI_TBL*2)
__GLOBAL_INI_NEXT:
	LPM
	ADIW R30,1
	MOV  R1,R0
	LPM
	ADIW R30,1
	MOV  R22,R30
	MOV  R23,R31
	MOV  R31,R0
	MOV  R30,R1
	SBIW R30,0
	BREQ __GLOBAL_INI_END
	LPM
	ADIW R30,1
	MOV  R26,R0
	LPM
	ADIW R30,1
	MOV  R27,R0
	LPM
	ADIW R30,1
	MOV  R24,R0
	LPM
	ADIW R30,1
	MOV  R25,R0
__GLOBAL_INI_LOOP:
	LPM
	ADIW R30,1
	ST   X+,R0
	SBIW R24,1
	BRNE __GLOBAL_INI_LOOP
	MOV  R30,R22
	MOV  R31,R23
	RJMP __GLOBAL_INI_NEXT
__GLOBAL_INI_END:

;STACK POINTER INITIALIZATION
	LDI  R30,LOW(0x25F)
	OUT  SPL,R30
	LDI  R30,HIGH(0x25F)
	OUT  SPH,R30

;DATA STACK POINTER INITIALIZATION
	LDI  R28,LOW(0xDF)
	LDI  R29,HIGH(0xDF)

	RJMP _main

	.ESEG
	.ORG 1

	.DSEG
	.ORG 0xE0
;       1 /*********************************************
;       2 This program was produced by the
;       3 CodeWizardAVR V1.23.7a Light
;       4 Automatic Program Generator
;       5 © Copyright 1998-2002 HP InfoTech s.r.l.
;       6 http://www.hpinfotech.ro
;       7 e-mail:office@hpinfotech.ro
;       8 
;       9 Project : 
;      10 Version : 
;      11 Date    : 02/04/2003
;      12 Author  : License Site 1..6, Remi TREUFFET
;      13 Company : Lycee PierreEmileMARTIN, Bourges
;      14 Comments: 
;      15 
;      16 
;      17 Chip type           : AT90S8535
;      18 Clock frequency     : 4,000000 MHz
;      19 Memory model        : Small
;      20 Internal SRAM size  : 512
;      21 External SRAM size  : 0
;      22 Data Stack size     : 128
;      23 *********************************************/
;      24 
;      25 #include <90s8535.h>
;      26 // CodeVisionAVR C Compiler
;      27 // (C) 1998-2000 Pavel Haiduc, HP InfoTech S.R.L.
;      28 
;      29 // I/O registers definitions for the AT90S8535
;      30 
;      31 #ifndef _90S8535_INCLUDED_
;      32 #define _90S8535_INCLUDED_
;      33 
;      34 #pragma used+
;      35 sfrb ADCL=4;
;      36 sfrb ADCH=5;
;      37 sfrw ADCW=4;      // 16 bit access
;      38 sfrb ADCSR=6;
;      39 sfrb ADMUX=7;
;      40 sfrb ACSR=8;
;      41 sfrb UBRR=9;
;      42 sfrb UCR=0xa;
;      43 sfrb USR=0xb;
;      44 sfrb UDR=0xc;
;      45 sfrb SPCR=0xd;
;      46 sfrb SPSR=0xe;
;      47 sfrb SPDR=0xf;
;      48 sfrb PIND=0x10;
;      49 sfrb DDRD=0x11;
;      50 sfrb PORTD=0x12;
;      51 sfrb PINC=0x13;
;      52 sfrb DDRC=0x14;
;      53 sfrb PORTC=0x15;
;      54 sfrb PINB=0x16;
;      55 sfrb DDRB=0x17;
;      56 sfrb PORTB=0x18;
;      57 sfrb PINA=0x19;
;      58 sfrb DDRA=0x1a;
;      59 sfrb PORTA=0x1b;
;      60 sfrb EECR=0x1c;
;      61 sfrb EEDR=0x1d;
;      62 sfrb EEARL=0x1e;
;      63 sfrb EEARH=0x1f;
;      64 sfrw EEAR=0x1e;   // 16 bit access
;      65 sfrb WDTCR=0x21;
;      66 sfrb ASSR=0x22;
;      67 sfrb OCR2=0x23;
;      68 sfrb TCNT2=0x24;
;      69 sfrb TCCR2=0x25;
;      70 sfrb ICR1L=0x26;
;      71 sfrb ICR1H=0x27;
;      72 sfrw ICR1=0x26;   // 16 bit access
;      73 sfrb OCR1BL=0x28;
;      74 sfrb OCR1BH=0x29;
;      75 sfrw OCR1B=0x28;  // 16 bit access
;      76 sfrb OCR1AL=0x2a;
;      77 sfrb OCR1AH=0x2b;
;      78 sfrw OCR1A=0x2a;  // 16 bit access
;      79 sfrb TCNT1L=0x2c;
;      80 sfrb TCNT1H=0x2d;
;      81 sfrw TCNT1=0x2c;  // 16 bit access
;      82 sfrb TCCR1B=0x2e;
;      83 sfrb TCCR1A=0x2f;
;      84 sfrb TCNT0=0x32;
;      85 sfrb TCCR0=0x33;
;      86 sfrb MCUSR=0x34;
;      87 sfrb MCUCR=0x35;
;      88 sfrb TIFR=0x38;
;      89 sfrb TIMSK=0x39;
;      90 sfrb GIFR=0x3a;
;      91 sfrb GIMSK=0x3b;
;      92 sfrb SPL=0x3d;
;      93 sfrb SPH=0x3e;
;      94 sfrb SREG=0x3f;
;      95 #pragma used-
;      96 
;      97 // Interrupt vectors definitions
;      98 
;      99 #define EXT_INT0 2
;     100 #define EXT_INT1 3
;     101 #define TIM2_COMP 4
;     102 #define TIM2_OVF 5
;     103 #define TIM1_CAPT 6
;     104 #define TIM1_COMPA 7
;     105 #define TIM1_COMPB 8
;     106 #define TIM1_OVF 9
;     107 #define TIM0_OVF 10
;     108 #define SPI_STC 11
;     109 #define UART_RXC 12
;     110 #define UART_DRE 13
;     111 #define UART_TXC 14
;     112 #define ADC_INT 15
;     113 #define EE_RDY 16
;     114 #define ANA_COMP 17
;     115 
;     116 #endif
;     117 
;     118 #include <delay.h>
;     119 // CodeVisionAVR C Compiler
;     120 // (C) 1998-2000 Pavel Haiduc, HP InfoTech S.R.L.
;     121 
;     122 #ifndef _DELAY_INCLUDED_
;     123 #define _DELAY_INCLUDED_
;     124 
;     125 #pragma used+
;     126 
;     127 void delay_us(unsigned int n);
;     128 void delay_ms(unsigned int n);
;     129 
;     130 #pragma used-
;     131 
;     132 #endif
;     133 #include <stdio.h>
;     134 // CodeVisionAVR C Compiler
;     135 // (C) 1998-2002 Pavel Haiduc, HP InfoTech S.R.L.
;     136 
;     137 // Prototypes for standard I/O functions
;     138 
;     139 #ifndef _STDIO_INCLUDED_
;     140 #define _STDIO_INCLUDED_
;     141 
;     142 #ifndef NULL
;     143 #define NULL 0
;     144 #endif
;     145 
;     146 #ifndef EOF
;     147 #define EOF -1
;     148 #endif
;     149 
;     150 #pragma used+
;     151 
;     152 char getchar(void);
;     153 void putchar(char c);
;     154 void puts(char *str);
;     155 void putsf(char flash *str);
;     156 
;     157 #ifdef _MODEL_TINY_
;     158 char *gets(char *str,unsigned char len);
;     159 #endif
;     160 
;     161 #ifdef _MODEL_SMALL_
;     162 char *gets(char *str,unsigned int len);
;     163 #endif
;     164 
;     165 #pragma parptr+
;     166 void printf(char flash *fmtstr);
;     167 void sprintf(char *str, char flash *fmtstr);
;     168 #pragma parptr-
;     169 
;     170 signed char scanf(char flash *fmtstr,...);
;     171 signed char sscanf(char *str, char flash *fmtstr,...);
;     172 
;     173 #ifdef _DEBUG_TERMINAL_IO_
;     174 // Used for AVR Studio Terminal I/O
;     175 // DON'T CHANGE!
;     176 #pragma warn-
;     177 #pragma keep+
;     178 void _c_getchar(void) {}
;     179 
;     180 char getchar(void)
;     181 {
;     182 #asm
;     183      push  r16
;     184      push  r17
;     185 __getchar0:
;     186 #endasm
;     187 _c_getchar();
;     188 #asm
;     189      cpi   r17,0xff
;     190      breq  __getchar0
;     191      mov   r30,r16
;     192      pop   r17
;     193      pop   r16
;     194 #endasm
;     195 }
;     196 
;     197 void _c_putchar(void) {}
;     198 
;     199 void putchar(char c)
;     200 {
;     201 #asm
;     202     mov   r30,r16
;     203     ld    r16,y
;     204 #endasm
;     205 _c_putchar();
;     206 #asm
;     207     mov   r16,r30
;     208 #endasm
;     209 }
;     210 #pragma keep-
;     211 
;     212 #ifdef _WARNINGS_ON_
;     213 #pragma warn+
;     214 #endif
;     215 
;     216 #endif
;     217 #pragma used-
;     218 
;     219 #pragma library stdio.lib
;     220 
;     221 #endif
;     222 
;     223 
;     224 // Read the AD conversion result
;     225 unsigned int read_adc(unsigned char adc_input)
;     226 {

	.CSEG
_read_adc:
;     227 ADMUX=adc_input;
	LD   R30,Y
	OUT  0x7,R30
;     228 // Start the AD conversion
;     229 ADCSR|=0x40;
	SBI  0x6,6
;     230 // Wait for the AD conversion to complete
;     231 while ((ADCSR & 0x10)==0);
_0xD:
	SBIS 0x6,4
	RJMP _0xD
;     232 ADCSR|=0x10;
	SBI  0x6,4
;     233 return ADCW;
	IN   R30,0x4
	IN   R31,0x4+1
	ADIW R28,1
	RET
;     234 }
;     235 
;     236 // Declare your global variables here
;     237 
;     238 void main(void)
;     239 {
_main:
;     240 // Declare your local variables here
;     241 float calcul_OCRIA;
;     242 int angle, position;
;     243 unsigned char i,capteur_1, capteur;
;     244 
;     245 // Input/Output Ports initialization
;     246 // Port A initialization
;     247 // Func0=In Func1=In Func2=In Func3=In Func4=In Func5=In Func6=In Func7=In 
;     248 // State0=P State1=P State2=P State3=P State4=P State5=P State6=T State7=T 
;     249 PORTA=0x3F;
	SBIW R28,5
;	calcul_OCRIA -> Y+1
;	angle -> R16,R17
;	position -> R18,R19
;	i -> R20
;	capteur_1 -> R21
;	capteur -> Y+0
	LDI  R30,LOW(63)
	OUT  0x1B,R30
;     250 DDRA=0x00;
	CLR  R30
	OUT  0x1A,R30
;     251 
;     252 // Port B initialization
;     253 // Func0=In Func1=In Func2=In Func3=In Func4=In Func5=In Func6=In Func7=In 
;     254 // State0=T State1=T State2=T State3=T State4=T State5=T State6=T State7=T 
;     255 PORTB=0x00;
	OUT  0x18,R30
;     256 DDRB=0x00;
	OUT  0x17,R30
;     257 
;     258 // Port C initialization
;     259 // Func0=In Func1=In Func2=In Func3=In Func4=In Func5=In Func6=In Func7=In 
;     260 // State0=T State1=T State2=T State3=T State4=T State5=T State6=T State7=T 
;     261 PORTC=0x00;
	OUT  0x15,R30
;     262 DDRC=0x00;
	OUT  0x14,R30
;     263 
;     264 // Port D initialization
;     265 // Func0=In Func1=In Func2=In Func3=In Func4=In Func5=Out Func6=In Func7=In 
;     266 // State0=T State1=T State2=T State3=T State4=T State5=0 State6=T State7=T 
;     267 PORTD=0x00;
	OUT  0x12,R30
;     268 DDRD=0x20;
	LDI  R30,LOW(32)
	OUT  0x11,R30
;     269 
;     270 // Timer/Counter 0 initialization
;     271 // Clock source: System Clock
;     272 // Clock value: Timer 0 Stopped
;     273 TCCR0=0x00;
	CLR  R30
	OUT  0x33,R30
;     274 TCNT0=0x00;
	OUT  0x32,R30
;     275 
;     276 // Timer/Counter 1 initialization
;     277 // Clock source: System Clock
;     278 // Clock value: 62,500 kHz
;     279 // Mode: Ph. correct PWM top=00FFh
;     280 // OC1A output: Non-Inv.
;     281 // OC1B output: Discon.
;     282 // Noise Canceler: Off
;     283 // Input Capture on Falling Edge
;     284 TCCR1A=0xC1;
	LDI  R30,LOW(193)
	OUT  0x2F,R30
;     285 TCCR1B=0x03;
	LDI  R30,LOW(3)
	OUT  0x2E,R30
;     286 TCNT1H=0x00;
	CLR  R30
	OUT  0x2D,R30
;     287 TCNT1L=0x00;
	OUT  0x2C,R30
;     288 OCR1AH=0x00;
	OUT  0x2B,R30
;     289 OCR1AL=0x00;
	OUT  0x2A,R30
;     290 OCR1BH=0x00;
	OUT  0x29,R30
;     291 OCR1BL=0x00;
	OUT  0x28,R30
;     292 
;     293 // Timer/Counter 2 initialization
;     294 // Clock source: System Clock
;     295 // Clock value: Timer 2 Stopped
;     296 // Mode: Normal top=FFh
;     297 // OC2 output: Disconnected
;     298 ASSR=0x00;
	OUT  0x22,R30
;     299 TCCR2=0x00;
	OUT  0x25,R30
;     300 TCNT2=0x00;
	OUT  0x24,R30
;     301 OCR2=0x00;
	OUT  0x23,R30
;     302 
;     303 // External Interrupt(s) initialization
;     304 // INT0: Off
;     305 // INT1: Off
;     306 GIMSK=0x00;
	OUT  0x3B,R30
;     307 MCUCR=0x00;
	OUT  0x35,R30
;     308 
;     309 // Timer(s)/Counter(s) Interrupt(s) initialization
;     310 TIMSK=0x00;
	OUT  0x39,R30
;     311 
;     312 // Analog Comparator initialization
;     313 // Analog Comparator: Off
;     314 // Analog Comparator Input Capture by Timer/Counter 1: Off
;     315 // Analog Comparator Output: Off
;     316 ACSR=0x80;
	LDI  R30,LOW(128)
	OUT  0x8,R30
;     317 
;     318 // ADC initialization
;     319 // ADC Clock frequency: 31,250 kHz
;     320 ADCSR=0x87;
	LDI  R30,LOW(135)
	OUT  0x6,R30
;     321 
;     322 while (1)
_0x11:
;     323       { 
;     324       	// Recherche Umax entre 0 et -60°
;     325         delay_ms(3000);
	RCALL SUBOPT_0x0
;     326         angle = -60;
	__GETWRN 16,17,65476
;     327 	for (i=0;i<24;i++)
	LDI  R20,LOW(0)
_0x15:
	CPI  R20,24
	BRSH _0x16
;     328          { 
;     329 	   calcul_OCRIA = 255*(1-((1.356e-3*angle)+0.183)); 
	RCALL SUBOPT_0x1
;     330            OCR1A = calcul_OCRIA;
;     331            capteur=read_adc(6)/4;
;     332            if (capteur> capteur_1) 
	BRSH _0x17
;     333            	{ 
;     334            	 capteur_1 = capteur;
	LDD  R21,Y+0
;     335            	 position = angle;
	__MOVEWRR 18,19,16,17
;     336            	}	 
;     337            delay_ms(1000);
_0x17:
	RCALL SUBOPT_0x2
;     338            angle = angle + 5; 
	__ADDWRN 16,17,5
;     339          }
	SUBI R20,-1
	RJMP _0x15
_0x16:
;     340          
;     341         // Recherche Umax entre 0 et -60°   
;     342         delay_ms(3000);
	RCALL SUBOPT_0x0
;     343         angle = 60;
	__GETWRN 16,17,60
;     344 	for (i=0;i<24;i++)
	LDI  R20,LOW(0)
_0x19:
	CPI  R20,24
	BRSH _0x1A
;     345          { 
;     346            calcul_OCRIA = 255*(1-((1.356e-3*angle)+0.183)); 
	RCALL SUBOPT_0x1
;     347            OCR1A = calcul_OCRIA;
;     348            capteur=read_adc(6)/4;
;     349            if (capteur> capteur_1) 
	BRSH _0x1B
;     350            	{ 
;     351            	 capteur_1 = capteur;
	LDD  R21,Y+0
;     352            	 position = angle;
	__MOVEWRR 18,19,16,17
;     353            	}
;     354            delay_ms(1000);
_0x1B:
	RCALL SUBOPT_0x2
;     355            angle = angle - 5; 
	__SUBWRN 16,17,5
;     356          }
	SUBI R20,-1
	RJMP _0x19
_0x1A:
;     357          
;     358          // Meilleur position
;     359          calcul_OCRIA = 255*(1-((1.356e-3*position)+0.183));
	__GETW1R 18,19
	__GETD2N 0x3AB1BBCF
	RCALL __CWD1
	RCALL __CDF1
	RCALL __MULF12
	__GETD2N 0x3E3B645A
	RCALL __ADDF12
	__GETD2N 0x3F800000
	RCALL __SWAPD12
	RCALL __SUBF12
	__GETD2N 0x437F0000
	RCALL __MULF12
	__PUTD1S 1
;     360          OCR1A = calcul_OCRIA;
	RCALL __CFD1
	OUT  0x2A+1,R31
	OUT  0x2A,R30
;     361          delay_ms(10000);  
	LDI  R30,LOW(10000)
	LDI  R31,HIGH(10000)
	ST   -Y,R31
	ST   -Y,R30
	RCALL _delay_ms
;     362       }; 
	RJMP _0x11
;     363 }
	ADIW R28,5
_0x1C:
	RJMP _0x1C
_getchar:
     sbis usr,rxc
     rjmp _getchar
     in   r30,udr
	RET
_putchar:
     sbis usr,udre
     rjmp _putchar
     ld   r30,y
     out  udr,r30
	ADIW R28,1
	RET

	.DSEG
_cc_G2:
	.BYTE 0x1
_pp_G2:
	.BYTE 0x2

	.CSEG

;OPTIMIZER ADDED SUBROUTINE, CALLED 2 TIMES
SUBOPT_0x0:
	LDI  R30,LOW(3000)
	LDI  R31,HIGH(3000)
	ST   -Y,R31
	ST   -Y,R30
	RJMP _delay_ms

;OPTIMIZER ADDED SUBROUTINE, CALLED 2 TIMES
SUBOPT_0x1:
	__GETW1R 16,17
	__GETD2N 0x3AB1BBCF
	RCALL __CWD1
	RCALL __CDF1
	RCALL __MULF12
	__GETD2N 0x3E3B645A
	RCALL __ADDF12
	__GETD2N 0x3F800000
	RCALL __SWAPD12
	RCALL __SUBF12
	__GETD2N 0x437F0000
	RCALL __MULF12
	__PUTD1S 1
	RCALL __CFD1
	OUT  0x2A+1,R31
	OUT  0x2A,R30
	LDI  R30,LOW(6)
	ST   -Y,R30
	RCALL _read_adc
	RCALL __LSRW2
	ST   Y,R30
	LD   R26,Y
	CP   R21,R26
	RET

;OPTIMIZER ADDED SUBROUTINE, CALLED 2 TIMES
SUBOPT_0x2:
	LDI  R30,LOW(1000)
	LDI  R31,HIGH(1000)
	ST   -Y,R31
	ST   -Y,R30
	RJMP _delay_ms

_isdigit:
	ldi  r30,1
	ld   r31,y+
	cpi  r31,'0'
	brlo __isdigit0
	cpi  r31,'9'+1
	brlo __isdigit1
__isdigit0:
	clr  r30
__isdigit1:
	ret

_isspace:
	ldi  r30,1
	ld   r31,y+
	cpi  r31,' '
	breq __isspace1
	cpi  r31,9
	breq __isspace1
	cpi  r31,13
	breq __isspace1
	clr  r30
__isspace1:
	ret

_delay_ms:
	ld   r30,y+
	ld   r31,y+
	adiw r30,0
	breq __delay_ms1
__delay_ms0:
	__DELAY_USW 0x3E8
	wdr
	sbiw r30,1
	brne __delay_ms0
__delay_ms1:
	ret

__ANEGD1:
	COM  R30
	COM  R31
	COM  R22
	COM  R23
	SUBI R30,-1
	SBCI R31,-1
	SBCI R22,-1
	SBCI R23,-1
	RET

__LSRW2:
	LSR  R31
	ROR  R30
	LSR  R31
	ROR  R30
	RET

__CWD1:
	CLR  R22
	CLR  R23
	SBRS R31,7
	RET
	SER  R22
	SER  R23
	RET

__SWAPD12:
	MOV  R1,R24
	MOV  R24,R22
	MOV  R22,R1
	MOV  R1,R25
	MOV  R25,R23
	MOV  R23,R1

__SWAPW12:
	MOV  R1,R27
	MOV  R27,R31
	MOV  R31,R1

__SWAPB12:
	MOV  R1,R26
	MOV  R26,R30
	MOV  R30,R1
	RET

__REPACK:
	LDI  R21,0x80
	EOR  R21,R23
	BRNE __REPACK0
	PUSH R21
	RJMP __ZERORES
__REPACK0:
	CPI  R21,0xFF
	BREQ __REPACK1
	LSL  R22
	LSL  R0
	ROR  R21
	ROR  R22
	MOV  R23,R21
	RET
__REPACK1:
	PUSH R21
	TST  R0
	BRMI __REPACK2
	RJMP __MAXRES
__REPACK2:
	RJMP __MINRES

__UNPACK:
	LDI  R21,0x80
	MOV  R1,R25
	AND  R1,R21
	LSL  R24
	ROL  R25
	EOR  R25,R21
	LSL  R21
	ROR  R24

__UNPACK1:
	LDI  R21,0x80
	MOV  R0,R23
	AND  R0,R21
	LSL  R22
	ROL  R23
	EOR  R23,R21
	LSL  R21
	ROR  R22
	RET

__CFD1:
	PUSH R21
	RCALL __UNPACK1
	CPI  R23,0x80
	BREQ __CFD10
	LDI  R21,22
	SUB  R21,R23
	BRPL __CFD11
	RJMP __MAXRES
__CFD11:
	CPI  R21,24
	BRLO __CFD12
__CFD10:
	RJMP __ZERORES
__CFD12:
	CLR  R23
__CFD13:
	CPI  R21,8
	BRLO __CFD14
	MOV  R30,R31
	MOV  R31,R22
	MOV  R22,R23
	SUBI R21,8
	RJMP __CFD13
__CFD14:
	TST  R21
	BREQ __CFD16
__CFD15:
	LSR  R23
	ROR  R22
	ROR  R31
	ROR  R30
	DEC  R21
	BRNE __CFD15
__CFD16:
	CLR  R23
	TST  R0
	BRPL __CFD17
	RCALL __NEGMAN1
	SER  R23
__CFD17:
	POP  R21
	RET

__CDF1U:
	SET
	RJMP __CDF1U0
__CDF1:
	CLT
__CDF1U0:
	SBIW R30,0
	SBCI R22,0
	SBCI R23,0
	BREQ __CDF10
	CLR  R0
	BRTS __CDF11
	TST  R23
	BRPL __CDF11
	COM  R0
	RCALL __ANEGD1
__CDF11:
	MOV  R1,R23
	LDI  R23,30
	TST  R1
__CDF12:
	BRMI __CDF13
	DEC  R23
	LSL  R30
	ROL  R31
	ROL  R22
	ROL  R1
	RJMP __CDF12
__CDF13:
	MOV  R30,R31
	MOV  R31,R22
	MOV  R22,R1
	PUSH R21
	RCALL __REPACK
	POP  R21
__CDF10:
	RET

__SWAPACC:
	MOV  R21,R30
	MOV  R30,R26
	MOV  R26,R21
	MOV  R21,R31
	MOV  R31,R27
	MOV  R27,R21
	MOV  R21,R22
	MOV  R22,R24
	MOV  R24,R21
	MOV  R21,R23
	MOV  R23,R25
	MOV  R25,R21
	MOV  R21,R0
	MOV  R0,R1
	MOV  R1,R21
	RET

__UADD12:
	ADD  R30,R26
	ADC  R31,R27
	ADC  R22,R24
	RET

__NEGMAN1:
	COM  R30
	COM  R31
	COM  R22
	SUBI R30,-1
	SBCI R31,-1
	SBCI R22,-1
	RET

__SUBF12:
	PUSH R21
	RCALL __UNPACK
	CPI  R25,0x80
	BREQ __ADDF129
	LDI  R21,0x80
	EOR  R1,R21

	RJMP __ADDF120

__ADDF12:
	PUSH R21
	RCALL __UNPACK
	CPI  R25,0x80
	BREQ __ADDF129

__ADDF120:
	CPI  R23,0x80
	BREQ __ADDF128
__ADDF121:
	MOV  R21,R23
	SUB  R21,R25
	BRVS __ADDF129
	BRPL __ADDF122
	RCALL __SWAPACC
	RJMP __ADDF121
__ADDF122:
	CPI  R21,24
	BRLO __ADDF123
	CLR  R26
	CLR  R27
	CLR  R24
__ADDF123:
	CPI  R21,8
	BRLO __ADDF124
	MOV  R26,R27
	MOV  R27,R24
	CLR  R24
	SUBI R21,8
	RJMP __ADDF123
__ADDF124:
	TST  R21
	BREQ __ADDF126
__ADDF125:
	LSR  R24
	ROR  R27
	ROR  R26
	DEC  R21
	BRNE __ADDF125
__ADDF126:
	MOV  R21,R0
	EOR  R21,R1
	BRMI __ADDF127
	RCALL __UADD12
	BRCC __ADDF129
	ROR  R22
	ROR  R31
	ROR  R30
	INC  R23
	BRVC __ADDF129
	RJMP __MAXRES
__ADDF128:
	RCALL __SWAPACC
__ADDF129:
	RCALL __REPACK
	POP  R21
	RET
__ADDF127:
	SUB  R30,R26
	SBC  R31,R27
	SBC  R22,R24
	BREQ __ZERORES
	BRCC __ADDF1210
	COM  R0
	RCALL __NEGMAN1
__ADDF1210:
	TST  R22
	BRMI __ADDF129
	LSL  R30
	ROL  R31
	ROL  R22
	DEC  R23
	BRVC __ADDF1210

__MINRES:
	SER  R30
	SER  R31
	LDI  R22,0x7F
	SER  R23
	POP  R21
	RET

__ZERORES:
	CLR  R30
	CLR  R31
	CLR  R22
	CLR  R23
	POP  R21
	RET

__MAXRES:
	SER  R30
	SER  R31
	LDI  R22,0x7F
	LDI  R23,0x7F
	POP  R21
	RET

__MULF12:
	PUSH R21
	RCALL __UNPACK
	CPI  R23,0x80
	BREQ __ZERORES
	CPI  R25,0x80
	BREQ __ZERORES
	EOR  R0,R1
	SEC
	ADC  R23,R25
	BRVC __MULF124
	BRLT __ZERORES
__MULF125:
	TST  R0
	BRMI __MINRES
	RJMP __MAXRES
__MULF124:
	PUSH R19
	PUSH R20
	CLR  R1
	CLR  R19
	CLR  R20
	CLR  R21
	LDI  R25,24
__MULF120:
	LSL  R19
	ROL  R20
	ROL  R21
	ROL  R30
	ROL  R31
	ROL  R22
	BRCC __MULF121
	ADD  R19,R26
	ADC  R20,R27
	ADC  R21,R24
	ADC  R30,R1
	ADC  R31,R1
	ADC  R22,R1
__MULF121:
	DEC  R25
	BRNE __MULF120
	POP  R20
	POP  R19
	TST  R22
	BRMI __MULF122
	LSL  R21
	ROL  R30
	ROL  R31
	ROL  R22
	RJMP __MULF123
__MULF122:
	INC  R23
	BRVS __MULF125
__MULF123:
	RCALL __REPACK
	POP  R21
	RET

	.ORG 0x00

;INTERRUPT VECTORS
	RJMP __RESET
	RJMP 0
	RJMP 0
	RJMP 0
	RJMP 0
	RJMP 0
	RJMP 0
	RJMP 0
	RJMP 0
	RJMP 0
	RJMP 0
	RJMP 0
	RJMP 0
	RJMP 0
	RJMP 0
	RJMP 0
	RJMP 0
